Re: [Xen-devel] [PATCH 7/7] vm-event/arm: implement support for control-register write vm-events

[Corneliu ZUZU <czuzu@xxxxxxxxxxxxxxx>]

On 6/17/2016 1:36 PM, Corneliu ZUZU wrote:
> On 6/16/2016 7:49 PM, Julien Grall wrote:
> > Hello Corneliu,
> >
> > On 16/06/16 15:13, Corneliu ZUZU wrote:
> >
> > > +    case MWS_TTBCR:
> > > +        MWS_EMUL(TTBCR);
> > > +        break;
> > > +    default:
> > > +        break;
> > > +    }
> > > +
> > > +    w->status = MWS_NOWRITE;
> > > +}
> > > +
> > > +static inline void vcpu_enter_adjust_traps(struct vcpu *v)
> > > +{
> > > +    register_t old_hcr, hcr;
> > > +
> > > +    hcr = (old_hcr = READ_SYSREG(HCR_EL2));
> > > +
> > > +    if ( unlikely(0 != 
> > > v->domain->arch.monitor.write_ctrlreg_enabled) )
> > > +        hcr |= HCR_TVM;
> > > +    else
> > > +        hcr &= ~HCR_TVM;
> > > +
> > > +    if ( unlikely(hcr != old_hcr) )
> > > +    {
> > > +        WRITE_SYSREG(hcr, HCR_EL2);
> > > +        isb();
> > > +    }
> > The HCR register is also updated in p2m_restore_state to set 
> > HCR_EL2.RW. I would prefer to have a single place where HCR is updated.
> > Maybe we should store the HCR value per-domain?
> Yes, that would be nice. Will look into that for v2.
Julien,

I was trying to implement having HCR stored in arch_domain or arch_vcpu 
as suggested above and I'm a bit confused about the code in 
p2m_restore_state.
I'm hoping you can provide some feedback on this matter. Here's the 
current implementation of the function:
    void p2m_restore_state(struct vcpu *n)
    {
        register_t hcr;

        hcr = READ_SYSREG(HCR_EL2);
        WRITE_SYSREG(hcr & ~HCR_VM, HCR_EL2);
        isb();

        p2m_load_VTTBR(n->domain);
        isb();

        if ( is_32bit_domain(n->domain) )
            hcr &= ~HCR_RW;
        else
            hcr |= HCR_RW;

        WRITE_SYSREG(n->arch.sctlr, SCTLR_EL1);
        isb();

        WRITE_SYSREG(hcr, HCR_EL2);
        isb();
    }

First of all, I see the HCR_VM bit being unset (=0) but I don't quite 
understand why and even more peculiar is the fact that I couldn't find 
any place where the bit is set (=1) again.
Secondly, why this order of operations? More specifically, why is 
p2m_load_VTTBR done after the HCR_VM bit is unset and before the HCR_RW 
bit is set/unset? Can't we write HCR only once here?
And finally, I see the function is called by construct_dom0. The code 
there looks like:
    /*
     * The following loads use the domain's p2m and require current to
     * be a vcpu of the domain, temporarily switch
     */
    saved_current = current;
    p2m_restore_state(v);
    [...]
    /* Now that we are done restore the original p2m and current. */
    set_current(saved_current);
    p2m_restore_state(saved_current);

I suppose the significant changes p2m_restore_state does for the code in 
between ("[...]") is setting VTTBR & SCTLR which are used by translation 
functions such as gvirt_to_maddr (which seems to use PAR_EL1).
What I don't grasp is what effect setting the VTTBR has if HCR.HCR_VM is 
unset and left unset...
Thanks,
Corneliu.

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