[Xen-devel] [PATCH 3/3] xen/arm: drivers: scif: Add clock auto detection

[Dirk Behme <dirk.behme@xxxxxxxxxxxx>]

Besides the 14MHz external clock, the SCIF might be clocked by an
internal 66MHz clock. Detect this clock based on the SCIF_DL register
being 0 (internal clock) or != 0 (external clock).

Signed-off-by: Dirk Behme <dirk.behme@xxxxxxxxxxxx>
---
 xen/drivers/char/scif-uart.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c
index bc157fe..678f46b 100644
--- a/xen/drivers/char/scif-uart.c
+++ b/xen/drivers/char/scif-uart.c
@@ -107,8 +107,19 @@ static void __init scif_uart_init_preirq(struct 
serial_port *port)
     scif_readw(uart, SCIF_SCLSR);
     scif_writew(uart, SCIF_SCLSR, 0);
 
-    /* Select Baud rate generator output as a clock source */
-    scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10);
+    /*
+     * Select Baud rate generator output as a clock source
+     * The clock source can be an internal or external clock.
+     * Depending on this the DL register is either 0 or contains
+     * the divisor. I.e. we can use this to detect the clock
+     * source and based on this can configure the CKE[1:0] bits
+     * of the SCSCR register.
+     */
+    if ( scif_readw(uart, SCIF_DL) )
+        scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10); /* External clk */
+    else
+        scif_writew(uart, SCIF_SCSCR, SCSCR_CKE00); /* Internal clk */
+
 
     /* Setup protocol format and Baud rate, select Asynchronous mode */
     val = 0;
-- 
2.8.0


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