Re: [Xen-devel] [PATCH v4 15/26] x86/cpu: Rework Intel masking/faulting setup

[Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>]

> + * Context switch levelling state to the next domain.  A parameter of NULL is
> + * used to context switch to the default host state, and is used by the 
> BSP/AP
> + * startup code.
> + */
> +static void intel_ctxt_switch_levelling(const struct domain *nextd)
> +{
> +     struct cpuidmasks *these_masks = &this_cpu(cpuidmasks);
> +     const struct cpuidmasks *masks = &cpuidmask_defaults;
> +

Same question as on the AMD - would it make sense to add an ASSERT
to make sure that !nextd && system_state != SYS_STATE_active?

.. snip..

> +static void __init noinline intel_init_levelling(void)
> +{
> +     if (opt_cpu_info) {
> +             printk(XENLOG_INFO "Levelling caps: %#x\n", levelling_caps);
> +
> +             if (!cpu_has_cpuid_faulting)
> +                     printk(XENLOG_INFO
> +                            "MSR defaults: 1d 0x%08x, 1c 0x%08x, e1d 0x%08x, 
> "
> +                            "e1c 0x%08x, Da1 0x%08x\n",
> +                            (uint32_t)(cpuidmask_defaults._1cd >> 32),
> +                            (uint32_t)cpuidmask_defaults._1cd,
> +                            (uint32_t)(cpuidmask_defaults.e1cd >> 32),
> +                            (uint32_t)cpuidmask_defaults.e1cd,
> +                            (uint32_t)cpuidmask_defaults.Da1);

Perhaps shift Da1 as there is no need in seeing the upper bits?

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