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Re: [Xen-devel] [PATCH] xen/arm64: Fix incorrect memory region size in TCR2_EL2





On 14/03/16 14:37, Shanker Donthineni wrote:
HI Jullen,

Hi Shanker,

On 03/12/2016 07:13 AM, Julien Grall wrote:
Hi Shanker,

On 11/03/2016 04:28, Shanker Donthineni wrote:
The maximum and minimum values for T0SZ depend on level of
translation as per AArch64 Virtual Memory System Architecture.
The current code sets T0SZ to zero in TCR2_EL2 which is not

s/TCR2_EL2/TCR_EL2/


Sorry for typo, I will fix in next patch

valid and also might see unexpected behavior on some CPUs.

Can you provide more details?


We are not able to boot XEN on Qualcomm platforms and CPU hung after
after executing this line of ASM code.

I looked at the specification, programming the field T0SZ to 0 is valid
(see D4-1463 ARM DDI 0487A.b):

"For a stage 1 translation
The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller
than 16 then the implementation behaves as if the field were programmed
to 16 for all purposes other than reading back the value of the field."


The behavior of T0SZ=0 is described in ARM spec (DDI0487A_h, page 1752). Still 
I think setting
the T0SZ to 48bit is the right fix similar to LINUX KVM64 EL2 code.

For a stage 1 translation
The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 
then it is
IMPLEMENTATION DEFINED whether:

• The implementation behaves as if the field were programmed to 16 for all 
purposes other than
reading back the value of the field.

• Any use of the TxSZ value generates a stage 1 Level 0 Translation fault.

Sorry, I was looking at an older version of the ARM ARM where only a single possible behavior was described. So this change looks valid to me.

Can you please mention the version and the section of the spec in the commit message?

Regards,

--
Julien Grall

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