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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2.5 31/30] Fix PV guest XSAVE handling with levelling
Will be folded into appropriate patches in v3.
---
xen/arch/x86/cpu/amd.c | 15 +++++++++++++--
xen/arch/x86/domctl.c | 15 +++++++++++++++
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index deb98ea..3e345fe 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -265,7 +265,15 @@ static void __init noinline amd_init_levelling(void)
edx &= m->edx;
}
- cpuidmask_defaults._1cd &= ((uint64_t)ecx << 32) | edx;
+ /* Fast-forward bits - Must be set. */
+ if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
+ ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE);
+ edx |= cpufeat_mask(X86_FEATURE_APIC);
+
+ /* Allow the HYPERVISOR bit to be set via guest policy. */
+ ecx |= cpufeat_mask(X86_FEATURE_HYPERVISOR);
+
+ cpuidmask_defaults._1cd = ((uint64_t)ecx << 32) | edx;
}
if ((levelling_caps & LCAP_e1cd) == LCAP_e1cd) {
@@ -281,7 +289,10 @@ static void __init noinline amd_init_levelling(void)
edx &= m->ext_edx;
}
- cpuidmask_defaults.e1cd &= ((uint64_t)ecx << 32) | edx;
+ /* Fast-forward bits - Must be set. */
+ edx |= cpufeat_mask(X86_FEATURE_APIC);
+
+ cpuidmask_defaults.e1cd = ((uint64_t)ecx << 32) | edx;
}
if ((levelling_caps & LCAP_7ab0) == LCAP_7ab0) {
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index f06bc02..613bb5c 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -103,6 +103,15 @@ static void update_domain_cpuid_info(struct domain *d,
case X86_VENDOR_AMD:
mask &= ((uint64_t)ecx << 32) | edx;
+
+ /* Fast-forward bits - Must be set. */
+ if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
+ ecx = cpufeat_mask(X86_FEATURE_OSXSAVE);
+ else
+ ecx = 0;
+ edx = cpufeat_mask(X86_FEATURE_APIC);
+
+ mask |= ((uint64_t)ecx << 32) | edx;
break;
}
@@ -170,6 +179,12 @@ static void update_domain_cpuid_info(struct domain *d,
case X86_VENDOR_AMD:
mask &= ((uint64_t)ecx << 32) | edx;
+
+ /* Fast-forward bits - Must be set. */
+ ecx = 0;
+ edx = cpufeat_mask(X86_FEATURE_APIC);
+
+ mask |= ((uint64_t)ecx << 32) | edx;
break;
}
--
2.1.4
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