Advisory to Users on system topology enumeration This utility is for demonstration purpose only. It assumes the hardware topology configuration within a coherent domain does not change during the life of an OS session. If an OS support advanced features that can change hardware topology configurations, more sophisticated adaptation may be necessary to account for the hardware configuration change that might have added and reduced the number of logical processors being managed by the OS. User should also`be aware that the system topology enumeration algorithm is based on the assumption that CPUID instruction will return raw data reflecting the native hardware configuration. When an application runs inside a virtual machine hosted by a Virtual Machine Monitor (VMM), any CPUID instructions issued by an app (or a guest OS) are trapped by the VMM and it is the VMM's responsibility and decision to emulate/supply CPUID return data to the virtual machines. When deploying topology enumeration code based on querying CPUID inside a VM environment, the user must consult with the VMM vendor on how an VMM will emulate CPUID instruction relating to topology enumeration. Software visible enumeration in the system: Number of logical processors visible to the OS: 16 Number of logical processors visible to this process: 16 Number of processor cores visible to this process: 8 Number of physical packages visible to this process: 1 Hierarchical counts by levels of processor topology: # of cores in package 0 visible to this process: 8 . # of logical processors in Core 0 visible to this process: 2 . # of logical processors in Core 1 visible to this process: 2 . # of logical processors in Core 2 visible to this process: 2 . # of logical processors in Core 3 visible to this process: 2 . # of logical processors in Core 4 visible to this process: 2 . # of logical processors in Core 5 visible to this process: 2 . # of logical processors in Core 6 visible to this process: 2 . # of logical processors in Core 7 visible to this process: 2 . Affinity masks per SMT thread, per core, per package: Individual: P:0, C:0, T:0 --> 1 P:0, C:0, T:1 --> 2 Core-aggregated: P:0, C:0 --> 3 Individual: P:0, C:1, T:0 --> 4 P:0, C:1, T:1 --> 8 Core-aggregated: P:0, C:1 --> c Individual: P:0, C:2, T:0 --> 10 P:0, C:2, T:1 --> 20 Core-aggregated: P:0, C:2 --> 30 Individual: P:0, C:3, T:0 --> 40 P:0, C:3, T:1 --> 80 Core-aggregated: P:0, C:3 --> c0 Individual: P:0, C:4, T:0 --> 100 P:0, C:4, T:1 --> 200 Core-aggregated: P:0, C:4 --> 300 Individual: P:0, C:5, T:0 --> 400 P:0, C:5, T:1 --> 800 Core-aggregated: P:0, C:5 --> c00 Individual: P:0, C:6, T:0 --> 1z3 P:0, C:6, T:1 --> 2z3 Core-aggregated: P:0, C:6 --> 3z3 Individual: P:0, C:7, T:0 --> 4z3 P:0, C:7, T:1 --> 8z3 Core-aggregated: P:0, C:7 --> cz3 Pkg-aggregated: P:0 --> ffff APIC ID listings from affinity masks OS cpu 0, Affinity mask 000001 - apic id 0 OS cpu 1, Affinity mask 000002 - apic id 1 OS cpu 2, Affinity mask 000004 - apic id 2 OS cpu 3, Affinity mask 000008 - apic id 3 OS cpu 4, Affinity mask 000010 - apic id 4 OS cpu 5, Affinity mask 000020 - apic id 5 OS cpu 6, Affinity mask 000040 - apic id 6 OS cpu 7, Affinity mask 000080 - apic id 7 OS cpu 8, Affinity mask 000100 - apic id 8 OS cpu 9, Affinity mask 000200 - apic id 9 OS cpu 10, Affinity mask 000400 - apic id a OS cpu 11, Affinity mask 000800 - apic id b OS cpu 12, Affinity mask 001000 - apic id c OS cpu 13, Affinity mask 002000 - apic id d OS cpu 14, Affinity mask 004000 - apic id e OS cpu 15, Affinity mask 008000 - apic id f Package 0 Cache and Thread details Box Description: Cache is cache level designator Size is cache size OScpu# is cpu # as seen by OS Core is core#[_thread# if > 1 thread/core] inside socket AffMsk is AffinityMask(extended hex) for core and thread CmbMsk is Combined AffinityMask(extended hex) for hw threads sharing cache CmbMsk will differ from AffMsk if > 1 hw_thread/cache Extended Hex replaces trailing zeroes with 'z#' where # is number of zeroes (so '8z5' is '0x800000') L1D is Level 1 Data cache, size(KBytes)= 32, Cores/cache= 2, Caches/package= 8 L1I is Level 1 Instruction cache, size(KBytes)= 32, Cores/cache= 2, Caches/package= 8 L2 is Level 2 Unified cache, size(KBytes)= 256, Cores/cache= 2, Caches/package= 8 L3 is Level 3 Unified cache, size(KBytes)= 25600, Cores/cache= 16, Caches/package= 1 +-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ Cache | L1D | L1D | L1D | L1D | L1D | L1D | L1D | L1D | Size | 32K | 32K | 32K | 32K | 32K | 32K | 32K | 32K | OScpu#| 0 1| 2 3| 4 5| 6 7| 8 9| 10 11| 12 13| 14 15| Core |c0_t0 c0_t1|c1_t0 c1_t1|c2_t0 c2_t1|c3_t0 c3_t1|c4_t0 c4_t1|c5_t0 c5_t1|c6_t0 c6_t1|c7_t0 c7_t1| AffMsk| 1 2| 4 8| 10 20| 40 80| 100 200| 400 800| 1z3 2z3| 4z3 8z3| CmbMsk| 3 | c | 30 | c0 | 300 | c00 | 3z3 | cz3 | +-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ Cache | L1I | L1I | L1I | L1I | L1I | L1I | L1I | L1I | Size | 32K | 32K | 32K | 32K | 32K | 32K | 32K | 32K | +-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ Cache | L2 | L2 | L2 | L2 | L2 | L2 | L2 | L2 | Size | 256K | 256K | 256K | 256K | 256K | 256K | 256K | 256K | +-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ Cache | L3 | Size | 25M | CmbMsk| ffff | +-----------------------------------------------------------------------------------------------+