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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH RFC 04/31] xen/x86: Mask out unknown features from Xen's capabilities
If Xen doesn't know about a feature, it is unsafe for use and should be
deliberately hidden from Xen's capabilities.
This doesn't make a practical difference yet, but will make a difference
later when the guest featuresets are seeded from the host featureset.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
---
xen/arch/x86/cpu/common.c | 1 +
xen/arch/x86/cpuid/cpuid-private.h | 26 +++++++++
xen/arch/x86/cpuid/cpuid.c | 105 +++++++++++++++++++++++++++++++++++++
3 files changed, 132 insertions(+)
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 3496b13..5bdb4b3 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -324,6 +324,7 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
* we do "generic changes."
*/
for (i = 0; i < XEN_NR_FEATURESET_ENTRIES; ++i) {
+ c->x86_capability[i] &= known_features[i];
c->x86_capability[i] ^= inverted_features[i];
}
diff --git a/xen/arch/x86/cpuid/cpuid-private.h
b/xen/arch/x86/cpuid/cpuid-private.h
index c8b47b3..a4d582c 100644
--- a/xen/arch/x86/cpuid/cpuid-private.h
+++ b/xen/arch/x86/cpuid/cpuid-private.h
@@ -10,6 +10,32 @@
#endif
+/* Mask of bits which are shared between 1d and e1d. */
+#define SHARED_1d \
+ (cpufeat_mask(X86_FEATURE_FPU) | \
+ cpufeat_mask(X86_FEATURE_VME) | \
+ cpufeat_mask(X86_FEATURE_DE) | \
+ cpufeat_mask(X86_FEATURE_PSE) | \
+ cpufeat_mask(X86_FEATURE_TSC) | \
+ cpufeat_mask(X86_FEATURE_MSR) | \
+ cpufeat_mask(X86_FEATURE_PAE) | \
+ cpufeat_mask(X86_FEATURE_MCE) | \
+ cpufeat_mask(X86_FEATURE_CX8) | \
+ cpufeat_mask(X86_FEATURE_APIC) | \
+ cpufeat_mask(X86_FEATURE_MTRR) | \
+ cpufeat_mask(X86_FEATURE_PGE) | \
+ cpufeat_mask(X86_FEATURE_MCA) | \
+ cpufeat_mask(X86_FEATURE_CMOV) | \
+ cpufeat_mask(X86_FEATURE_PAT) | \
+ cpufeat_mask(X86_FEATURE_PSE36) | \
+ cpufeat_mask(X86_FEATURE_MMX) | \
+ cpufeat_mask(X86_FEATURE_FXSR))
+
+/*
+ * Bitmap of features known to Xen.
+ */
+extern const uint32_t known_features[XEN_NR_FEATURESET_ENTRIES];
+
/*
* Bitmap of "anti" features which have their representation inverted when
* stored as a featureset.
diff --git a/xen/arch/x86/cpuid/cpuid.c b/xen/arch/x86/cpuid/cpuid.c
index 1578725..6ee9ce2 100644
--- a/xen/arch/x86/cpuid/cpuid.c
+++ b/xen/arch/x86/cpuid/cpuid.c
@@ -1,5 +1,110 @@
#include "cpuid-private.h"
+const uint32_t known_features[XEN_NR_FEATURESET_ENTRIES] =
+{
+ [cpufeat_word(X86_FEATURE_FPU)] = (SHARED_1d |
+ cpufeat_mask(X86_FEATURE_SEP) |
+ cpufeat_mask(X86_FEATURE_PN) |
+ cpufeat_mask(X86_FEATURE_CLFLSH) |
+ cpufeat_mask(X86_FEATURE_DS) |
+ cpufeat_mask(X86_FEATURE_ACPI) |
+ cpufeat_mask(X86_FEATURE_XMM) |
+ cpufeat_mask(X86_FEATURE_XMM2) |
+ cpufeat_mask(X86_FEATURE_SELFSNOOP) |
+ cpufeat_mask(X86_FEATURE_HT) |
+ cpufeat_mask(X86_FEATURE_ACC) |
+ cpufeat_mask(X86_FEATURE_IA64) |
+ cpufeat_mask(X86_FEATURE_PBE)),
+
+ [cpufeat_word(X86_FEATURE_XMM3)] = (cpufeat_mask(X86_FEATURE_XMM3)
|
+ cpufeat_mask(X86_FEATURE_PCLMULQDQ)
|
+ cpufeat_mask(X86_FEATURE_DTES64)
|
+ cpufeat_mask(X86_FEATURE_MWAIT)
|
+ cpufeat_mask(X86_FEATURE_DSCPL)
|
+ cpufeat_mask(X86_FEATURE_VMXE)
|
+ cpufeat_mask(X86_FEATURE_SMXE)
|
+ cpufeat_mask(X86_FEATURE_EST)
|
+ cpufeat_mask(X86_FEATURE_TM2)
|
+ cpufeat_mask(X86_FEATURE_SSSE3)
|
+ cpufeat_mask(X86_FEATURE_CID)
|
+ cpufeat_mask(X86_FEATURE_FMA)
|
+ cpufeat_mask(X86_FEATURE_CX16)
|
+ cpufeat_mask(X86_FEATURE_XTPR)
|
+ cpufeat_mask(X86_FEATURE_PDCM)
|
+ cpufeat_mask(X86_FEATURE_PCID)
|
+ cpufeat_mask(X86_FEATURE_DCA)
|
+ cpufeat_mask(X86_FEATURE_SSE4_1)
|
+ cpufeat_mask(X86_FEATURE_SSE4_2)
|
+ cpufeat_mask(X86_FEATURE_X2APIC)
|
+ cpufeat_mask(X86_FEATURE_MOVBE)
|
+ cpufeat_mask(X86_FEATURE_POPCNT)
|
+ cpufeat_mask(X86_FEATURE_TSC_DEADLINE)
|
+ cpufeat_mask(X86_FEATURE_AES)
|
+ cpufeat_mask(X86_FEATURE_XSAVE)
|
+ cpufeat_mask(X86_FEATURE_OSXSAVE)
|
+ cpufeat_mask(X86_FEATURE_AVX)
|
+ cpufeat_mask(X86_FEATURE_F16C)
|
+ cpufeat_mask(X86_FEATURE_RDRAND)
|
+ cpufeat_mask(X86_FEATURE_HYPERVISOR)),
+
+ [cpufeat_word(X86_FEATURE_SYSCALL)] = (SHARED_1d |
+ cpufeat_mask(X86_FEATURE_SYSCALL) |
+ cpufeat_mask(X86_FEATURE_MP) |
+ cpufeat_mask(X86_FEATURE_NX) |
+ cpufeat_mask(X86_FEATURE_MMXEXT) |
+ cpufeat_mask(X86_FEATURE_FFXSR) |
+ cpufeat_mask(X86_FEATURE_PAGE1GB) |
+ cpufeat_mask(X86_FEATURE_RDTSCP) |
+ cpufeat_mask(X86_FEATURE_LM) |
+ cpufeat_mask(X86_FEATURE_3DNOWEXT) |
+ cpufeat_mask(X86_FEATURE_3DNOW)),
+
+ [cpufeat_word(X86_FEATURE_LAHF_LM)] = (cpufeat_mask(X86_FEATURE_LAHF_LM)
|
+
cpufeat_mask(X86_FEATURE_CMP_LEGACY) |
+ cpufeat_mask(X86_FEATURE_SVM)
|
+ cpufeat_mask(X86_FEATURE_EXTAPIC)
|
+
cpufeat_mask(X86_FEATURE_CR8_LEGACY) |
+ cpufeat_mask(X86_FEATURE_ABM)
|
+ cpufeat_mask(X86_FEATURE_SSE4A)
|
+
cpufeat_mask(X86_FEATURE_MISALIGNSSE) |
+
cpufeat_mask(X86_FEATURE_3DNOWPREFETCH) |
+ cpufeat_mask(X86_FEATURE_OSVW)
|
+ cpufeat_mask(X86_FEATURE_IBS)
|
+ cpufeat_mask(X86_FEATURE_XOP)
|
+ cpufeat_mask(X86_FEATURE_SKINIT)
|
+ cpufeat_mask(X86_FEATURE_WDT)
|
+ cpufeat_mask(X86_FEATURE_LWP)
|
+ cpufeat_mask(X86_FEATURE_FMA4)
|
+
cpufeat_mask(X86_FEATURE_NODEID_MSR) |
+ cpufeat_mask(X86_FEATURE_TBM)
|
+ cpufeat_mask(X86_FEATURE_TOPOEXT)
|
+ cpufeat_mask(X86_FEATURE_DBEXT)
|
+ cpufeat_mask(X86_FEATURE_MWAITX)),
+
+ [cpufeat_word(X86_FEATURE_XSAVEOPT)] = (cpufeat_mask(X86_FEATURE_XSAVEOPT)
|
+ cpufeat_mask(X86_FEATURE_XSAVEC)
|
+ cpufeat_mask(X86_FEATURE_XGETBV1)
|
+ cpufeat_mask(X86_FEATURE_XSAVES)),
+
+ [cpufeat_word(X86_FEATURE_FSGSBASE)] = (cpufeat_mask(X86_FEATURE_FSGSBASE)
|
+
cpufeat_mask(X86_FEATURE_TSC_ADJUST) |
+ cpufeat_mask(X86_FEATURE_BMI1)
|
+ cpufeat_mask(X86_FEATURE_HLE)
|
+ cpufeat_mask(X86_FEATURE_AVX2)
|
+ cpufeat_mask(X86_FEATURE_SMEP)
|
+ cpufeat_mask(X86_FEATURE_BMI2)
|
+ cpufeat_mask(X86_FEATURE_ERMS)
|
+ cpufeat_mask(X86_FEATURE_INVPCID)
|
+ cpufeat_mask(X86_FEATURE_RTM)
|
+ cpufeat_mask(X86_FEATURE_CMT)
|
+ cpufeat_mask(X86_FEATURE_FPU_SEL)
|
+ cpufeat_mask(X86_FEATURE_MPX)
|
+ cpufeat_mask(X86_FEATURE_CAT)
|
+ cpufeat_mask(X86_FEATURE_RDSEED)
|
+ cpufeat_mask(X86_FEATURE_ADX)
|
+ cpufeat_mask(X86_FEATURE_SMAP)),
+};
+
const uint32_t inverted_features[XEN_NR_FEATURESET_ENTRIES] =
{
[cpufeat_word(X86_FEATURE_FPU_SEL)] = cpufeat_mask(X86_FEATURE_FPU_SEL),
--
2.1.4
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