[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 1/2] x86/VPMU: Support only versions 2 and 3 of architectural performance monitoring
We need to have at least version 2 since it's the first version to support various control and status registers (such as MSR_CORE_PERF_GLOBAL_CTRL) that VPMU relies on always having. With explicit testing for PMU version we can now remove CPUID model check. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> --- xen/arch/x86/cpu/vpmu_intel.c | 55 +++++++------------------------------------ 1 file changed, 8 insertions(+), 47 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index d5ea7fe..bb4ddcc 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -955,59 +955,20 @@ int vmx_vpmu_initialise(struct vcpu *v) int __init core2_vpmu_init(void) { u64 caps; + unsigned int version = 0; - if ( current_cpu_data.x86 != 6 ) + if ( current_cpu_data.cpuid_level >= 0xa ) + version = cpuid_eax(0xa) & 0xff; + if ( (version != 2) && (version != 3) ) { - printk(XENLOG_WARNING "VPMU: only family 6 is supported\n"); + printk(XENLOG_WARNING "VPMU: version %d is not supported\n", version); return -EINVAL; } - switch ( current_cpu_data.x86_model ) + if ( current_cpu_data.x86 != 6 ) { - /* Core2: */ - case 0x0f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ - case 0x16: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ - case 0x17: /* 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ - case 0x1d: /* six-core 45 nm xeon "Dunnington" */ - - case 0x2a: /* SandyBridge */ - case 0x2d: /* SandyBridge, "Romley-EP" */ - - /* Nehalem: */ - case 0x1a: /* 45 nm nehalem, "Bloomfield" */ - case 0x1e: /* 45 nm nehalem, "Lynnfield", "Clarksfield", "Jasper Forest" */ - case 0x2e: /* 45 nm nehalem-ex, "Beckton" */ - - /* Westmere: */ - case 0x25: /* 32 nm nehalem, "Clarkdale", "Arrandale" */ - case 0x2c: /* 32 nm nehalem, "Gulftown", "Westmere-EP" */ - case 0x2f: /* 32 nm Westmere-EX */ - - case 0x3a: /* IvyBridge */ - case 0x3e: /* IvyBridge EP */ - - /* Haswell: */ - case 0x3c: - case 0x3f: - case 0x45: - case 0x46: - - /* Broadwell */ - case 0x3d: - case 0x4f: - case 0x56: - - /* future: */ - case 0x4e: - - /* next gen Xeon Phi */ - case 0x57: - break; - - default: - printk(XENLOG_WARNING "VPMU: Unsupported CPU model %#x\n", - current_cpu_data.x86_model); - return -EINVAL; + printk(XENLOG_WARNING "VPMU: only family 6 is supported\n"); + return -EINVAL; } arch_pmc_cnt = core2_get_arch_pmc_count(); -- 1.8.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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