[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 3/6] xen: Drop empty __cpuinit annotation
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- CC: Jan Beulich <JBeulich@xxxxxxxx> CC: Ian Campbell <ian.campbell@xxxxxxxxxx> CC: Stefano Stabellini <stefano.stabellini@xxxxxxxxxx> --- xen/arch/arm/cpu.c | 2 +- xen/arch/arm/gic-hip04.c | 6 +++--- xen/arch/arm/gic-v2.c | 6 +++--- xen/arch/arm/gic-v3.c | 6 +++--- xen/arch/arm/gic.c | 4 ++-- xen/arch/arm/irq.c | 4 ++-- xen/arch/arm/mm.c | 2 +- xen/arch/arm/smpboot.c | 6 +++--- xen/arch/arm/time.c | 2 +- xen/arch/arm/traps.c | 2 +- xen/arch/x86/cpu/common.c | 18 +++++++++--------- xen/arch/x86/cpu/intel_cacheinfo.c | 4 ++-- xen/arch/x86/numa.c | 4 ++-- xen/arch/x86/x86_64/mmconf-fam10h.c | 2 +- xen/include/asm-arm/gic.h | 2 +- xen/include/asm-arm/mm.h | 4 ++-- xen/include/asm-arm/p2m.h | 2 +- xen/include/asm-arm/time.h | 2 +- xen/include/xen/config.h | 2 -- 19 files changed, 39 insertions(+), 41 deletions(-) diff --git a/xen/arch/arm/cpu.c b/xen/arch/arm/cpu.c index afc564f..d21651c 100644 --- a/xen/arch/arm/cpu.c +++ b/xen/arch/arm/cpu.c @@ -17,7 +17,7 @@ #include <asm/processor.h> -void __cpuinit identify_cpu(struct cpuinfo_arm *c) +void identify_cpu(struct cpuinfo_arm *c) { c->midr.bits = READ_SYSREG32(MIDR_EL1); c->mpidr.bits = READ_SYSREG(MPIDR_EL1); diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c index 310f35a..a42cf24 100644 --- a/xen/arch/arm/gic-hip04.c +++ b/xen/arch/arm/gic-hip04.c @@ -306,7 +306,7 @@ static void __init hip04gic_dist_init(void) writel_gicd(GICD_CTL_ENABLE, GICD_CTLR); } -static void __cpuinit hip04gic_cpu_init(void) +static void hip04gic_cpu_init(void) { int i; @@ -344,7 +344,7 @@ static void hip04gic_cpu_disable(void) writel_gicc(0x0, GICC_CTLR); } -static void __cpuinit hip04gic_hyp_init(void) +static void hip04gic_hyp_init(void) { uint32_t vtr; uint8_t nr_lrs; @@ -354,7 +354,7 @@ static void __cpuinit hip04gic_hyp_init(void) gicv2_info.nr_lrs = nr_lrs; } -static void __cpuinit hip04gic_hyp_disable(void) +static void hip04gic_hyp_disable(void) { writel_gich(0, GICH_HCR); } diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 01e36b5..793dca7 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -292,7 +292,7 @@ static void __init gicv2_dist_init(void) writel_gicd(GICD_CTL_ENABLE, GICD_CTLR); } -static void __cpuinit gicv2_cpu_init(void) +static void gicv2_cpu_init(void) { int i; @@ -330,7 +330,7 @@ static void gicv2_cpu_disable(void) writel_gicc(0x0, GICC_CTLR); } -static void __cpuinit gicv2_hyp_init(void) +static void gicv2_hyp_init(void) { uint32_t vtr; uint8_t nr_lrs; @@ -340,7 +340,7 @@ static void __cpuinit gicv2_hyp_init(void) gicv2_info.nr_lrs = nr_lrs; } -static void __cpuinit gicv2_hyp_disable(void) +static void gicv2_hyp_disable(void) { writel_gich(0, GICH_HCR); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 4fe0c37..a245b56 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -676,7 +676,7 @@ static int __init gicv3_populate_rdist(void) return -ENODEV; } -static int __cpuinit gicv3_cpu_init(void) +static int gicv3_cpu_init(void) { int i; uint32_t priority; @@ -737,7 +737,7 @@ static void gicv3_cpu_disable(void) isb(); } -static void __cpuinit gicv3_hyp_init(void) +static void gicv3_hyp_init(void) { uint32_t vtr; @@ -768,7 +768,7 @@ static int gicv3_secondary_cpu_init(void) return res; } -static void __cpuinit gicv3_hyp_disable(void) +static void gicv3_hyp_disable(void) { uint32_t hcr; diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 1e1e5ba..0b3f634 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -305,7 +305,7 @@ void smp_send_state_dump(unsigned int cpu) } /* Set up the per-CPU parts of the GIC for a secondary CPU */ -void __cpuinit gic_init_secondary_cpu(void) +void gic_init_secondary_cpu(void) { gic_hw_ops->secondary_init(); /* Clear LR mask for secondary cpus */ @@ -695,7 +695,7 @@ void gic_dump_info(struct vcpu *v) } } -void __cpuinit init_maintenance_interrupt(void) +void init_maintenance_interrupt(void) { request_irq(gic_hw_ops->info->maintenance_irq, 0, maintenance_interrupt, "irq-maintenance", NULL); diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 1f38605..d409abb 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -85,7 +85,7 @@ static int __init init_irq_data(void) return 0; } -static int __cpuinit init_local_irq_data(void) +static int init_local_irq_data(void) { int irq; @@ -124,7 +124,7 @@ void __init init_IRQ(void) BUG_ON(init_irq_data() < 0); } -void __cpuinit init_secondary_IRQ(void) +void init_secondary_IRQ(void) { BUG_ON(init_local_irq_data() < 0); } diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 8b6d915..47bfb27 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -620,7 +620,7 @@ int init_secondary_pagetables(int cpu) #endif /* MMU setup for secondary CPUS (which already have paging enabled) */ -void __cpuinit mmu_init_secondary_cpu(void) +void mmu_init_secondary_cpu(void) { /* From now on, no mapping may be both writable and executable. */ WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index a96cda2..00b2b2a 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -264,9 +264,9 @@ smp_prepare_cpus (unsigned int max_cpus) } /* Boot the current CPU */ -void __cpuinit start_secondary(unsigned long boot_phys_offset, - unsigned long fdt_paddr, - unsigned long hwid) +void start_secondary(unsigned long boot_phys_offset, + unsigned long fdt_paddr, + unsigned long hwid) { unsigned int cpuid = init_data.cpuid; diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 6207615..40f4758 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -230,7 +230,7 @@ static void check_timer_irq_cfg(unsigned int irq, const char *which) } /* Set up the timer interrupt on this CPU */ -void __cpuinit init_timer_interrupt(void) +void init_timer_interrupt(void) { /* Sensible defaults */ WRITE_SYSREG64(0, CNTVOFF_EL2); /* No VM-specific offset */ diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index c49bd3f..83744e8 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -99,7 +99,7 @@ static int debug_stack_lines = 40; integer_param("debug_stack_lines", debug_stack_lines); -void __cpuinit init_traps(void) +void init_traps(void) { /* Setup Hyp vector base */ WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 265fdbc..ff3ff51 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -70,7 +70,7 @@ static const struct cpu_dev *this_cpu = &default_cpu; bool_t opt_cpu_info; boolean_param("cpuinfo", opt_cpu_info); -int __cpuinit get_model_name(struct cpuinfo_x86 *c) +int get_model_name(struct cpuinfo_x86 *c) { unsigned int *v; char *p, *q; @@ -100,7 +100,7 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c) } -void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) +void display_cacheinfo(struct cpuinfo_x86 *c) { unsigned int dummy, ecx, edx, l2size; @@ -212,7 +212,7 @@ static void __init early_cpu_detect(void) paddr_bits = cpuid_eax(0x80000008) & 0xff; } -static void __cpuinit generic_identify(struct cpuinfo_x86 *c) +static void generic_identify(struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx, tmp; @@ -271,7 +271,7 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c) /* * This does the hard work of actually picking apart the CPU stuff... */ -void __cpuinit identify_cpu(struct cpuinfo_x86 *c) +void identify_cpu(struct cpuinfo_x86 *c) { int i; @@ -377,7 +377,7 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c) * Check for extended topology enumeration cpuid leaf 0xb and if it * exists, use it for cpu topology detection. */ -void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c) +void detect_extended_topology(struct cpuinfo_x86 *c) { unsigned int eax, ebx, ecx, edx, sub_index; unsigned int ht_mask_width, core_plus_mask_width; @@ -434,7 +434,7 @@ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c) } } -void __cpuinit detect_ht(struct cpuinfo_x86 *c) +void detect_ht(struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx; int index_msb, core_bits; @@ -509,7 +509,7 @@ unsigned int __init apicid_to_socket(unsigned int apicid) return apicid; } -void __cpuinit print_cpu_info(unsigned int cpu) +void print_cpu_info(unsigned int cpu) { const struct cpuinfo_x86 *c = cpu_data + cpu; const char *vendor = NULL; @@ -560,7 +560,7 @@ void __init early_cpu_init(void) * - Inserts TSS selector into regular and compat GDTs * - Loads GDT, IDT, TR then null LDT */ -void __cpuinit load_system_tables(void) +void load_system_tables(void) { unsigned int cpu = smp_processor_id(); unsigned long stack_bottom = get_stack_bottom(), @@ -613,7 +613,7 @@ void __cpuinit load_system_tables(void) * and IDT. We reload them nevertheless, this function acts as a * 'CPU state barrier', nothing should get across. */ -void __cpuinit cpu_init(void) +void cpu_init(void) { int cpu = smp_processor_id(); diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_cacheinfo.c index 980aa59..e505df1 100644 --- a/xen/arch/x86/cpu/intel_cacheinfo.c +++ b/xen/arch/x86/cpu/intel_cacheinfo.c @@ -104,7 +104,7 @@ int cpuid4_cache_lookup(int index, struct cpuid4_info *this_leaf) return 0; } -static int __cpuinit find_num_cache_leaves(void) +static int find_num_cache_leaves(void) { unsigned int eax, ebx, ecx, edx; union _cpuid4_leaf_eax cache_eax; @@ -119,7 +119,7 @@ static int __cpuinit find_num_cache_leaves(void) return i; } -unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) +unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c) { unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */ unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ diff --git a/xen/arch/x86/numa.c b/xen/arch/x86/numa.c index 6a8880f..886871f 100644 --- a/xen/arch/x86/numa.c +++ b/xen/arch/x86/numa.c @@ -290,12 +290,12 @@ void __init numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn) (u64)end_pfn << PAGE_SHIFT); } -__cpuinit void numa_add_cpu(int cpu) +void numa_add_cpu(int cpu) { cpumask_set_cpu(cpu, &node_to_cpumask[cpu_to_node(cpu)]); } -void __cpuinit numa_set_node(int cpu, nodeid_t node) +void numa_set_node(int cpu, nodeid_t node) { cpu_to_node[cpu] = node; } diff --git a/xen/arch/x86/x86_64/mmconf-fam10h.c b/xen/arch/x86/x86_64/mmconf-fam10h.c index 8bdd39e..ed0acb9 100644 --- a/xen/arch/x86/x86_64/mmconf-fam10h.c +++ b/xen/arch/x86/x86_64/mmconf-fam10h.c @@ -137,7 +137,7 @@ static void __init get_fam10h_pci_mmconf_base(void) fam10h_pci_mmconf_base = start; } -void __cpuinit fam10h_check_enable_mmcfg(void) +void fam10h_check_enable_mmcfg(void) { u64 val; bool_t print = opt_cpu_info; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 42a2eec..630bb33 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -237,7 +237,7 @@ extern void gic_inject(void); extern void gic_clear_pending_irqs(struct vcpu *v); extern int gic_events_need_delivery(void); -extern void __cpuinit init_maintenance_interrupt(void); +extern void init_maintenance_interrupt(void); extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq, unsigned int priority); extern void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq); diff --git a/xen/include/asm-arm/mm.h b/xen/include/asm-arm/mm.h index a95082e..69e770a 100644 --- a/xen/include/asm-arm/mm.h +++ b/xen/include/asm-arm/mm.h @@ -157,9 +157,9 @@ extern void setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr); extern void remove_early_mappings(void); /* Allocate and initialise pagetables for a secondary CPU. Sets init_ttbr to the * new page table */ -extern int __cpuinit init_secondary_pagetables(int cpu); +extern int init_secondary_pagetables(int cpu); /* Switch secondary CPUS to its own pagetables and finalise MMU setup */ -extern void __cpuinit mmu_init_secondary_cpu(void); +extern void mmu_init_secondary_cpu(void); /* Set up the xenheap: up to 1GB of contiguous, always-mapped memory. * Base must be 32MB aligned and size a multiple of 32MB. */ extern void setup_xenheap_mappings(unsigned long base_mfn, unsigned long nr_mfns); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 08bdce3..4c62725 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -122,7 +122,7 @@ void p2m_altp2m_check(struct vcpu *v, uint16_t idx) void p2m_vmid_allocator_init(void); /* Second stage paging setup, to be called on all CPUs */ -void __cpuinit setup_virt_paging(void); +void setup_virt_paging(void); /* Init the datastructures for later use by the p2m code */ int p2m_init(struct domain *d); diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index f99d6e8..5b9a31d 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -32,7 +32,7 @@ extern uint32_t timer_dt_clock_frequency; unsigned int timer_get_irq(enum timer_ppi ppi); /* Set up the timer interrupt on this CPU */ -extern void __cpuinit init_timer_interrupt(void); +extern void init_timer_interrupt(void); /* Counter value at boot time */ extern uint64_t boot_count; diff --git a/xen/include/xen/config.h b/xen/include/xen/config.h index 89a590e..9b4b6ef 100644 --- a/xen/include/xen/config.h +++ b/xen/include/xen/config.h @@ -84,8 +84,6 @@ #define mk_unsigned_long(x) x #endif /* !__ASSEMBLY__ */ -#define __cpuinit - #ifdef FLASK_ENABLE #define XSM_MAGIC 0xf97cff8c /* Maintain statistics on the access vector cache */ -- 2.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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