x86: drop further constant cpu_has_* predicates

EFER and SYSCALL are required on x86-64, and I think there's no point
in assuming there might be no TSC. A few other predicates are simply
unused. Of the ones left but constant I'm not convinced we should drop
them; for some of them we may actually better make them non-constant
(see also next patch in this series).

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/acpi/power.c
+++ b/xen/arch/x86/acpi/power.c
@@ -194,8 +194,7 @@ static int enter_state(u32 state)
     /* Restore CR4 and EFER from cached values. */
     cr4 = read_cr4();
     write_cr4(cr4 & ~X86_CR4_MCE);
-    if ( cpu_has_efer )
-        write_efer(read_efer());
+    write_efer(read_efer());
 
     device_power_up();
 
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -1130,7 +1130,7 @@ static void __devinit setup_APIC_timer(v
 
 static int __init calibrate_APIC_clock(void)
 {
-    unsigned long long t1 = 0, t2 = 0;
+    unsigned long long t1, t2;
     long tt1, tt2;
     long result;
     int i;
@@ -1157,8 +1157,7 @@ static int __init calibrate_APIC_clock(v
     /*
      * We wrapped around just now. Let's start:
      */
-    if (cpu_has_tsc)
-        t1 = rdtsc();
+    t1 = rdtsc();
     tt1 = apic_read(APIC_TMCCT);
 
     /*
@@ -1168,8 +1167,7 @@ static int __init calibrate_APIC_clock(v
         wait_8254_wraparound();
 
     tt2 = apic_read(APIC_TMCCT);
-    if (cpu_has_tsc)
-        t2 = rdtsc();
+    t2 = rdtsc();
 
     /*
      * The APIC bus clock counter is 32 bits only, it
@@ -1181,16 +1179,12 @@ static int __init calibrate_APIC_clock(v
 
     result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
 
-    if (cpu_has_tsc)
-        apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
-                    "%ld.%04ld MHz.\n",
-                    ((long)(t2-t1)/LOOPS)/(1000000/HZ),
-                    ((long)(t2-t1)/LOOPS)%(1000000/HZ));
-
-    apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
-                "%ld.%04ld MHz.\n",
-                result/(1000000/HZ),
-                result%(1000000/HZ));
+    apic_printk(APIC_VERBOSE, "..... CPU clock speed is %ld.%04ld MHz.\n",
+                ((long)(t2 - t1) / LOOPS) / (1000000 / HZ),
+                ((long)(t2 - t1) / LOOPS) % (1000000 / HZ));
+
+    apic_printk(APIC_VERBOSE, "..... host bus clock speed is %ld.%04ld MHz.\n",
+                result / (1000000 / HZ), result % (1000000 / HZ));
 
     /* set up multipliers for accurate timer code */
     bus_freq   = result*HZ;
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -86,17 +86,13 @@ trampoline_protmode_entry:
 
         /* Set up EFER (Extended Feature Enable Register). */
         mov     bootsym_rel(cpuid_ext_features,4,%edi)
-        test    $0x20100800,%edi /* SYSCALL/SYSRET, No Execute, Long Mode? */
-        jz      .Lskip_efer
         movl    $MSR_EFER,%ecx
         rdmsr
-        btsl    $_EFER_LME,%eax /* Long Mode      */
-        btsl    $_EFER_SCE,%eax /* SYSCALL/SYSRET */
-        btl     $20,%edi        /* No Execute?    */
+        or      $EFER_LME|EFER_SCE,%eax   /* Long Mode + SYSCALL/SYSRET */
+        bt      $X86_FEATURE_NX % 32,%edi /* No Execute? */
         jnc     1f
         btsl    $_EFER_NX,%eax  /* No Execute     */
 1:      wrmsr
-.Lskip_efer:
 
         mov     $(X86_CR0_PG | X86_CR0_AM | X86_CR0_WP | X86_CR0_NE |\
                   X86_CR0_ET | X86_CR0_MP | X86_CR0_PE), %eax
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -625,8 +625,7 @@ void __init noreturn __start_xen(unsigne
 
     parse_video_info();
 
-    if ( cpu_has_efer )
-        rdmsrl(MSR_EFER, this_cpu(efer));
+    rdmsrl(MSR_EFER, this_cpu(efer));
     asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
 
     /* We initialise the serial devices very early so we can get debugging. */
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -332,8 +332,7 @@ void start_secondary(void *unused)
     set_processor_id(cpu);
     set_current(idle_vcpu[cpu]);
     this_cpu(curr_vcpu) = idle_vcpu[cpu];
-    if ( cpu_has_efer )
-        rdmsrl(MSR_EFER, this_cpu(efer));
+    rdmsrl(MSR_EFER, this_cpu(efer));
 
     /*
      * Just as during early bootstrap, it is convenient here to disable
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -174,10 +174,8 @@
 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
 #define CPUID5_ECX_INTERRUPT_BREAK      0x2
 
-#define cpu_has_vme		0
 #define cpu_has_de		1
 #define cpu_has_pse		1
-#define cpu_has_tsc		1
 #define cpu_has_pge		1
 #define cpu_has_pat		1
 #define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)
@@ -186,15 +184,10 @@
 #define cpu_has_mmx		1
 #define cpu_has_xmm3		boot_cpu_has(X86_FEATURE_XMM3)
 #define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)
-#define cpu_has_syscall		1
 #define cpu_has_mp		1
 #define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)
-#define cpu_has_k6_mtrr		0
-#define cpu_has_cyrix_arr	0
-#define cpu_has_centaur_mcr	0
 #define cpu_has_clflush		boot_cpu_has(X86_FEATURE_CLFLSH)
 #define cpu_has_page1gb		boot_cpu_has(X86_FEATURE_PAGE1GB)
-#define cpu_has_efer		1
 #define cpu_has_fsgsbase	boot_cpu_has(X86_FEATURE_FSGSBASE)
 
 #define cpu_has_smep            boot_cpu_has(X86_FEATURE_SMEP)