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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v7 17/28] xen/arm: ITS: Add GITS registers emulation
From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
Emulate GITS* registers
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
---
v7: - Fixed wrong usage of vgic_regN* helpers
- coding styles and comments
- GITS_BASER0 is always overwritten with new value every time
it is updated.
v6: - Removed unrelated code of this patch
- Used vgic_regN_{read,write}
v4: - Removed GICR register emulation
---
xen/arch/arm/vgic-v3-its.c | 315 +++++++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/gic-its.h | 8 ++
xen/include/asm-arm/vits.h | 8 ++
3 files changed, 331 insertions(+)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index dba0b9e..0d97fcb 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++ b/xen/arch/arm/vgic-v3-its.c
@@ -36,6 +36,15 @@
//#define DEBUG_ITS
+/* GITS_PIDRn register values for ARM implementations */
+#define GITS_PIDR0_VAL (0x94)
+#define GITS_PIDR1_VAL (0xb4)
+#define GITS_PIDR2_VAL (0x3b)
+#define GITS_PIDR3_VAL (0x00)
+#define GITS_PIDR4_VAL (0x04)
+#define GITS_BASER0_INIT_VAL ((1UL << GITS_BASER_TYPE_SHIFT) | \
+ (sizeof(struct vitt) << \
+ GITS_BASER_ENTRY_SIZE_SHIFT))
#ifdef DEBUG_ITS
# define DPRINTK(fmt, args...) dprintk(XENLOG_DEBUG, fmt, ##args)
#else
@@ -503,6 +512,301 @@ err:
return 0;
}
+static inline void vits_spin_lock(struct vgic_its *vits)
+{
+ spin_lock(&vits->lock);
+}
+
+static inline void vits_spin_unlock(struct vgic_its *vits)
+{
+ spin_unlock(&vits->lock);
+}
+
+static int vgic_v3_gits_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ struct vgic_its *vits = v->domain->arch.vgic.vits;
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ uint64_t val;
+ uint32_t gits_reg;
+
+ gits_reg = info->gpa - vits->gits_base;
+ DPRINTK("%pv: vITS: GITS_MMIO_READ offset 0x%"PRIx32"\n", v, gits_reg);
+
+ switch ( gits_reg )
+ {
+ case GITS_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vits_spin_lock(vits);
+ /*
+ * vITS is always quiescent, has no translations in progress and
+ * completed all operations. So set quiescent by default.
+ */
+ *r = vgic_reg32_read(vits->ctrl, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GICV3_GICD_IIDR_VAL, info);
+ return 1;
+ case GITS_TYPER:
+ case GITS_TYPER + 4:
+ /*
+ * GITS_TYPER.HCC = max_vcpus + 1 (max collection supported)
+ * GITS_TYPER.Devbits = HW supported Devbits size
+ * GITS_TYPER.IDbits = HW supported IDbits size
+ * GITS_TYPER.PTA = 0 (Target addresses are linear processor numbers)
+ * GITS_TYPER.ITTSize = Size of struct vitt
+ * GITS_TYPER.Physical = 1
+ */
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ val = ((vits_get_max_collections(v->domain) << GITS_TYPER_HCC_SHIFT ) |
+ ((vits_hw.devID_bits - 1) << GITS_TYPER_DEVBITS_SHIFT) |
+ ((vits_hw.eventID_bits - 1) << GITS_TYPER_IDBITS_SHIFT) |
+ ((sizeof(struct vitt) - 1) << GITS_TYPER_ITT_SIZE_SHIFT) |
+ GITS_TYPER_PHYSICAL_LPIS);
+ *r = vgic_reg64_read(val, info);
+ return 1;
+ case 0x0010 ... 0x007c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- read ignored */
+ goto read_as_zero;
+ case GITS_CBASER:
+ case GITS_CBASER + 4:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ vits_spin_lock(vits);
+ *r = vgic_reg64_read(vits->cmd_base, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_CWRITER:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ vits_spin_lock(vits);
+ *r = vgic_reg64_read(vits->cmd_write, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_CWRITER + 4:
+ /* Bits[63:20] are RES0 */
+ goto read_as_zero_32;
+ case GITS_CREADR:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ *r = vgic_reg64_read(atomic_read(&vits->cmd_read), info);
+ return 1;
+ case GITS_CREADR + 4:
+ /* Bits[63:20] are RES0 */
+ goto read_as_zero_32;
+ case 0x0098 ... 0x009c:
+ case 0x00a0 ... 0x00fc:
+ case 0x0140 ... 0xbffc:
+ /* Reserved -- read ignored */
+ goto read_as_zero;
+ case GITS_BASER0:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ vits_spin_lock(vits);
+ *r = vgic_reg64_read(vits->baser0, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_BASER1 ... GITS_BASERN:
+ goto read_as_zero_64;
+ case GITS_PIDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR0_VAL, info);
+ return 1;
+ case GITS_PIDR1:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR1_VAL, info);
+ return 1;
+ case GITS_PIDR2:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR2_VAL, info);
+ return 1;
+ case GITS_PIDR3:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR3_VAL, info);
+ return 1;
+ case GITS_PIDR4:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR4_VAL, info);
+ return 1;
+ case GITS_PIDR5 ... GITS_PIDR7:
+ goto read_as_zero_32;
+ default:
+ dprintk(XENLOG_G_ERR,
+ "%pv: vITS: unhandled read r%d offset 0x%#08"PRIx32"\n",
+ v, dabt.reg, gits_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_G_ERR,
+ "%pv: vITS: bad read width %d r%d offset 0x%#08"PRIx32"\n",
+ v, dabt.size, dabt.reg, gits_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero_64:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ *r = 0;
+ return 1;
+read_as_zero_32:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+read_as_zero:
+ *r = 0;
+ return 1;
+}
+
+/*
+ * GITS_BASER.Type[58:56], GITS_BASER.Entry_size[55:48]
+ * and GITS_BASER.Shareability[11:10] are read-only,
+ * Only flat table is supported. So GITS_BASER.Indirect[62]
+ * is RAZ/WI.
+ * Mask those fields while emulating GITS_BASER reg.
+ * Shareability is set to 0x0 (Reserved) which is fixed.
+ * TODO: Support shareability as fixed value is deprecated
+ */
+#define GITS_BASER_MASK (~((0x7UL << GITS_BASER_TYPE_SHIFT) | \
+ (0x1UL << GITS_BASER_INDIRECT_SHIFT) | \
+ (0xffUL << GITS_BASER_ENTRY_SIZE_SHIFT) | \
+ (0x3UL << GITS_BASER_SHAREABILITY_SHIFT)))
+
+static int vgic_v3_gits_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ struct vgic_its *vits = v->domain->arch.vgic.vits;
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ int ret;
+ uint32_t gits_reg, sz, psz;
+ uint64_t val;
+
+ gits_reg = info->gpa - vits->gits_base;
+
+ DPRINTK("%pv: vITS: GITS_MMIO_WRITE offset 0x%"PRIx32"\n", v, gits_reg);
+ switch ( gits_reg )
+ {
+ case GITS_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vits_spin_lock(vits);
+ vgic_reg32_write(&vits->ctrl,
+ (*r & GITS_CTLR_ENABLE) | GITS_CTLR_QUIESCENT, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_IIDR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GITS_TYPER:
+ case GITS_TYPER + 4:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case 0x0010 ... 0x007c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- write ignored */
+ goto write_ignore;
+ case GITS_CBASER:
+ /* XXX: support 32-bit access */
+ if ( dabt.size != DABT_DOUBLE_WORD )
+ goto bad_width;
+ vits_spin_lock(vits);
+ if ( vits->ctrl & GITS_CTLR_ENABLE )
+ {
+ /* RO -- write ignored */
+ vits_spin_unlock(vits);
+ goto write_ignore;
+ }
+ vgic_reg64_write(&vits->cmd_base, *r, info);
+ if ( vits->cmd_base & GITS_BASER_VALID )
+ {
+ val = ((vits->cmd_base & GITS_BASER_PAGES_MASK_VAL) + 1) * SZ_4K;
+ vits->cmd_qsize = val;
+ atomic_set(&vits->cmd_read, 0);
+ }
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_CWRITER:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ vits_spin_lock(vits);
+ /* Only Bits[19:5] are writable */
+ vgic_reg64_write(&vits->cmd_write, (*r & 0xfffe0), info);
+ ret = 1;
+ /* CWRITER should be within command queue range */
+ if ( (vits->ctrl & GITS_CTLR_ENABLE) &&
+ (vits->cmd_write < vits->cmd_qsize) )
+ ret = vits_process_cmd(v, vits);
+ vits_spin_unlock(vits);
+ return ret;
+ case GITS_CWRITER + 4:
+ /* Bits[63:20] are RES0 */
+ goto write_ignore_32;
+ case GITS_CREADR:
+ /* RO -- write ignored */
+ goto write_ignore_64;
+ case 0x0098 ... 0x009c:
+ case 0x00a0 ... 0x00fc:
+ case 0x0140 ... 0xbffc:
+ /* Reserved -- write ignored */
+ goto write_ignore;
+ case GITS_BASER0:
+ /* Support only 64-bit access */
+ if ( dabt.size != DABT_DOUBLE_WORD )
+ goto bad_width;
+ vits_spin_lock(vits);
+ /* RO -- write ignored if GITS_CTLR.Enable = 1 */
+ if ( vits->ctrl & GITS_CTLR_ENABLE )
+ {
+ vits_spin_unlock(vits);
+ goto write_ignore;
+ }
+ val = GITS_BASER0_INIT_VAL | (*r & GITS_BASER_MASK);
+ vgic_reg64_write(&vits->baser0, val, info);
+ vits->dt_ipa = vits->baser0 & GITS_BASER_PA_MASK;
+ psz = (vits->baser0 >> GITS_BASER_PAGE_SIZE_SHIFT) &
+ GITS_BASER_PAGE_SIZE_MASK_VAL;
+ if ( psz == GITS_BASER_PAGE_SIZE_4K_VAL )
+ sz = 4;
+ else if ( psz == GITS_BASER_PAGE_SIZE_16K_VAL )
+ sz = 16;
+ else
+ /* 0x11 and 0x10 are treated as 64K size */
+ sz = 64;
+
+ vits->dt_size = (vits->baser0 & GITS_BASER_PAGES_MASK_VAL) * sz *
SZ_1K;
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_BASER1 ... GITS_BASERN:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ goto write_ignore;
+ case GITS_PIDR7 ... GITS_PIDR0:
+ /* RO -- write ignored */
+ goto write_ignore_32;
+ default:
+ dprintk(XENLOG_G_ERR,
+ "%pv vITS: unhandled write r%d offset 0x%#08"PRIx32"\n",
+ v, dabt.reg, gits_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_G_ERR,
+ "%pv: vITS: bad write width %d r%d offset 0x%#08"PRIx32"\n",
+ v, dabt.size, dabt.reg, gits_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore_64:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ return 1;
+write_ignore_32:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+write_ignore:
+ return 1;
+}
+
+static const struct mmio_handler_ops vgic_gits_mmio_handler = {
+ .read_handler = vgic_v3_gits_mmio_read,
+ .write_handler = vgic_v3_gits_mmio_write,
+};
+
int vits_domain_init(struct domain *d)
{
struct vgic_its *vits;
@@ -534,6 +838,17 @@ int vits_domain_init(struct domain *d)
for ( i = 0; i < vits_get_max_collections(d); i++ )
vits->collections[i].target_address = INVALID_PADDR;
+ vits->baser0 = GITS_BASER0_INIT_VAL;
+
+ /*
+ * Only one virtual ITS is provided to domain.
+ * Assign first physical ITS address to Dom0 virtual ITS.
+ */
+ vits->gits_base = vits_hw.phys_base;
+ vits->gits_size = vits_hw.phys_size;
+
+ register_mmio_handler(d, &vgic_gits_mmio_handler, vits->gits_base, SZ_64K);
+
return 0;
}
diff --git a/xen/include/asm-arm/gic-its.h b/xen/include/asm-arm/gic-its.h
index 57a652c..7936256 100644
--- a/xen/include/asm-arm/gic-its.h
+++ b/xen/include/asm-arm/gic-its.h
@@ -52,6 +52,8 @@
#define GITS_TYPER_IDBITS(r) ((((r) >> GITS_TYPER_IDBITS_SHIFT) &
0x1f) + 1)
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HCC_SHIFT (24)
+#define GITS_TYPER_PHYSICAL_LPIS (1UL)
+#define GITS_TYPER_ITT_SIZE_SHIFT (4)
#define GITS_CBASER_VALID (1UL << 63)
#define GITS_CBASER_nC (1UL << 59)
@@ -64,6 +66,7 @@
#define GITS_BASER_NR_REGS 8
#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_INDIRECT_SHIFT (62)
#define GITS_BASER_nC (1UL << 59)
#define GITS_BASER_WaWb (5UL << 59)
#define GITS_BASER_TYPE_SHIFT (56)
@@ -79,6 +82,10 @@
#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_4K_VAL (0)
+#define GITS_BASER_PAGE_SIZE_16K_VAL (1)
+#define GITS_BASER_PAGE_SIZE_MASK_VAL (0x3)
+#define GITS_BASER_PAGES_MASK_VAL (0xff)
#define GITS_BASER_TYPE_NONE 0
#define GITS_BASER_TYPE_DEVICE 1
#define GITS_BASER_TYPE_VCPU 2
@@ -87,6 +94,7 @@
#define GITS_BASER_TYPE_RESERVED5 5
#define GITS_BASER_TYPE_RESERVED6 6
#define GITS_BASER_TYPE_RESERVED7 7
+#define GITS_BASER_PA_MASK (0xfffffffff000UL)
/*
* ITS commands
diff --git a/xen/include/asm-arm/vits.h b/xen/include/asm-arm/vits.h
index 295cce4..dc02762 100644
--- a/xen/include/asm-arm/vits.h
+++ b/xen/include/asm-arm/vits.h
@@ -24,6 +24,10 @@
struct vgic_its
{
spinlock_t lock;
+ /* Emulation of BASER0 */
+ uint64_t baser0;
+ /* GICR ctrl register */
+ uint32_t ctrl;
/* Command queue base */
paddr_t cmd_base;
/* Command queue write pointer */
@@ -32,6 +36,10 @@ struct vgic_its
atomic_t cmd_read;
/* Command queue size */
unsigned long cmd_qsize;
+ /* ITS mmio physical base */
+ paddr_t gits_base;
+ /* ITS mmio physical size */
+ unsigned long gits_size;
/* vITT device table ipa */
paddr_t dt_ipa;
/* vITT device table size */
--
1.7.9.5
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