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Re: [Xen-devel] xhci_hcd intterrupt affinity in Dom0/DomU limited to single interrupt



>>> On 03.09.15 at 18:52, <ackerj67@xxxxxxxxx> wrote:
> On Thu, 2015-09-03 at 09:04 -0600, Jan Beulich wrote:
>> >>> On 03.09.15 at 14:04, <ackerj67@xxxxxxxxx> wrote:
>> >      I am still confused as to whether any device, or in this case 
>> > xhci_hcd, 
>> > can use more than one cpu at any given time. My     understanding based on 
>> > David's response is that it cannot due to the event channel mapping. The 
>> > device interrupt can be pinned     to a specific cpu by specifying the 
>> > affinity. I was hoping there was a way to allow the driver's interrupt to 
>> > be 
>> > scheduled to     use more than 1 CPU at any given time. 
>> 
>> The problem is that you're mixing up two things: devices and
>> interrupts. Any individual interrupt can only be serviced by a single
>> CPU at a time, due to the way event channels get bound. Any
>> individual device can have more than one interrupt (MSI or MSI-X),
>> and then each of these interrupts can be serviced on different
>> CPUs.
> 
> Thanks for clarifying. To the original question, with respect to my
> limited understanding of the event channels and interrupts, each
> interrupt can be serviced on a different CPU using irqbalance or setting
> the affinity manually, but the same interrupt cannot be serviced by more
> than 1 CPU at a time? If so, is there a way around the 1:1 binding when
> loading the Dom0 kernel - a flag or option to use the native interrupt
> scheduling for some set of or all 8 CPUs that the device can schedule
> interrupts on when not loading the Dom0? The xhci_hcd, as one example,
> seems to perform better when it is able to have interrupts serviced by
> multiple CPUs. 

I don't follow - we tell you this doesn't work (multiple times and
different people), and you ask yet another time whether this can
be made work? Just to make this very clear once again: Under Xen
(and leaving aside pure HVM guests), interrupt load from a single
device can be spread across CPUs only when the device uses
multiple interrupts.

Jan


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