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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [RFC 2/2] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers
On Tue, Aug 4, 2015 at 5:29 PM, Julien Grall <julien.grall@xxxxxxxxxx> wrote:
> Based on 8.1.3 (IHI 0069A), unless stated otherwise, the 64-bit registers
> supports both 32-bit and 64-bits access.
>
> All the registers we properly emulate (i.e not RAZ/WI) supports 32-bit access.
>
> For RAZ/WI, it's also seems to be the case but I'm not 100% sure. Anyway,
> emulating 32-bit access for them doesn't hurt. Note that we would need
> some extra care when they will be implemented (for instance GICR_PROPBASER).
>
> Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
> ---
> This is technically fixing boot of FreeBSD ARM64 guest with GICv3.
>
> AFAICT, Linux is not using 32-bit access in the GICv3 code expect
> for the ITS (which we don't support yet).
>
> So this patch is a good candidate for Xen 4.6, maybe only via
> backporting (i.e Xen 4.6.1) given that none of our supports guests OS
> needs them right now.
> ---
> xen/arch/arm/vgic-v3.c | 23 ++++++++++++++++-------
> 1 file changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 7ef7b16..0ef5d42 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -103,6 +103,15 @@ static struct vcpu *vgic_v3_get_target_vcpu(struct vcpu
> *v, unsigned int irq)
> return v_target;
> }
>
> +static inline bool vgic_reg64_check_access(struct hsr_dabt dabt)
> +{
> + /*
> + * 64 bits registers can be accessible using 32-bit and 64-bit unless
> + * stated otherwise (See 8.1.3 ARM IHI 0069A).
> + */
> + return ( dabt.size == DABT_DOUBLE_WORD || dabt.size == DABT_WORD );
> +}
> +
This function is required for virtual ITS driver. Better to move to vgic.h
> static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
> uint32_t gicr_reg)
> {
> @@ -123,7 +132,7 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v,
> mmio_info_t *info,
> {
> uint64_t typer, aff;
>
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> /* TBD: Update processor id in [23:8] when ITS support is added */
> aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
> MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
> @@ -209,7 +218,7 @@ bad_width:
> return 0;
>
> read_as_zero_64:
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> *r = 0;
> return 1;
>
> @@ -286,7 +295,7 @@ bad_width:
> return 0;
>
> write_ignore_64:
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( vgic_reg64_check_access(dabt) ) goto bad_width;
> return 1;
>
> write_ignore_32:
> @@ -774,7 +783,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,
> mmio_info_t *info)
> {
> uint64_t irouter;
>
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
> DABT_DOUBLE_WORD);
> if ( rank == NULL ) goto read_as_zero;
> @@ -850,7 +859,7 @@ bad_width:
> return 0;
>
> read_as_zero_64:
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( vgic_reg64_check_access(dabt) ) goto bad_width;
> *r = 0;
> return 1;
>
> @@ -935,7 +944,7 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v,
> mmio_info_t *info)
> /* SGI/PPI is RES0 */
> goto write_ignore_64;
> case GICD_IROUTER32 ... GICD_IROUTERN:
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
> DABT_DOUBLE_WORD);
> if ( rank == NULL ) goto write_ignore;
> @@ -1016,7 +1025,7 @@ write_ignore_32:
> return 1;
>
> write_ignore_64:
> - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + if ( vgic_reg64_check_access(dabt) ) goto bad_width;
> return 1;
>
> write_ignore:
> --
> 2.1.4
>
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