Re: [Xen-devel] [PATCH v4 15/17] xen/arm: ITS: Map ITS translation space

[Julien Grall <julien.grall@xxxxxxxxxx>]

Hi Vijay,

On 10/07/2015 09:42, vijay.kilari@xxxxxxxxx wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>
> ITS translation space contains GITS_TRANSLATOR
> register which is written by device to raise
> LPI. This space needs to mapped to every domain
> address space for all physical ITS available,
> so that device can access GITS_TRANSLATOR
> register using SMMU.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
> ---
>   xen/arch/arm/vgic-v3-its.c |   31 ++++++++++++++++++++++++++++++-
>   1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
> index 74e6ee7..301f065 100644
> --- a/xen/arch/arm/vgic-v3-its.c
> +++ b/xen/arch/arm/vgic-v3-its.c
> @@ -1082,6 +1082,35 @@ static const struct mmio_handler_ops 
> vgic_gits_mmio_handler = {
>       .write_handler = vgic_v3_gits_mmio_write,
>   };
>
> +/*
> + * Map the 64K ITS translation space in guest.
> + * This is required purely for device smmu writes.
> +*/
> +
> +static int vits_map_translation_space(struct domain *d)
> +{
> +    uint64_t addr, size;
> +    int ret;
> +
> +    addr = d->arch.vits->gits_base + SZ_64K;
> +    size = SZ_64K;
> +
> +    ret = map_mmio_regions(d,
> +                           paddr_to_pfn(addr & PAGE_MASK),
> +                           DIV_ROUND_UP(size, PAGE_SIZE),
> +                           paddr_to_pfn(addr & PAGE_MASK));
You are assuming a direct mapping in the guest memory for the ITS 
translation space.
While this may be true for dom0, it won't work for guests.

I'm fine if you don't handle this case for 4.6. Although I'd like to at 
least see a comment stating that we are using 1:1 mapping and an assert 
to check if the domain is using direct mapping (i.e 
is_domain_direct_mapped(d)).
Regards,

--
Julien Grall

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