x86/MSI-X: use qword MMIO access for address writes

Now that we support it for our guests, let's do so ourselves too.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/msi.c
+++ b/xen/arch/x86/msi.c
@@ -236,8 +236,7 @@ static bool_t read_msi_msg(struct msi_de
         if ( unlikely(!msix_memory_decoded(entry->dev,
                                            entry->msi_attrib.pos)) )
             return 0;
-        msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
-        msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
+        msg->address = readq(base + PCI_MSIX_ENTRY_ADDRESS_OFFSET);
         msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
         break;
     }
@@ -302,10 +301,7 @@ static int write_msi_msg(struct msi_desc
         if ( unlikely(!msix_memory_decoded(entry->dev,
                                            entry->msi_attrib.pos)) )
             return -ENXIO;
-        writel(msg->address_lo,
-               base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
-        writel(msg->address_hi,
-               base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
+        writeq(msg->address, base + PCI_MSIX_ENTRY_ADDRESS_OFFSET);
         writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
         break;
     }
--- a/xen/include/asm-x86/msi.h
+++ b/xen/include/asm-x86/msi.h
@@ -65,8 +65,13 @@ struct msi_info {
 };
 
 struct msi_msg {
-	u32	address_lo;	/* low 32 bits of msi message address */
-	u32	address_hi;	/* high 32 bits of msi message address */
+	union {
+		u64	address; /* message address */
+		struct {
+			u32	address_lo; /* message address low 32 bits */
+			u32	address_hi; /* message address high 32 bits */
+		};
+	};
 	u32	data;		/* 16 bits of msi message data */
 	u32	dest32;		/* used when Interrupt Remapping with EIM is enabled */
 };
--- a/xen/include/xen/pci_regs.h
+++ b/xen/include/xen/pci_regs.h
@@ -307,6 +307,7 @@
 #define  PCI_MSIX_BIRMASK	(7 << 0)
 
 #define PCI_MSIX_ENTRY_SIZE			16
+#define  PCI_MSIX_ENTRY_ADDRESS_OFFSET		0
 #define  PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET	0
 #define  PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET	4
 #define  PCI_MSIX_ENTRY_DATA_OFFSET		8