Re: [Xen-devel] [PATCH v2] x86: synchronize PCI config space access decoding

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 17.06.15 at 11:36, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 17/06/15 07:29, Jan Beulich wrote:
>>>>> On 16.06.15 at 20:26, <andrew.cooper3@xxxxxxxxxx> wrote:
>>> It turns out that MSR_AMD64_NB_CFG is unconditionally RAZ and has all
>>> writes discarded, so no HVM guest will ever be in a position to
>>> legitimately use AMD extended configuration access.
>> Where have you found that? The register (named NB_CFG1 in
>> newer families' BKGDs) is clearly r/w.
> 
> It is implemented as RAZ/write discard in the hvm msr intercept code,
> and appears to exist only to prevent the guest blowing up in a
> cross-vendor case.

Ah, that's something _we_ do. But the MSR write being discarded
doesn't mean a guest can't legitimately use extended accesses: I
don't think you expect OSes to read back what they wrote? I.e. an
OS enabling this functionality would read zero, write back the value
modified to have the bit set, and go on assuming extended
accesses are okay now.

Jan


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