[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v3 09/10] VT-d: use qword MMIO access for MSI address writes
Also make dmar_{read,write}q() actually do what their names suggest (we don't need to be concerned of 32-bit restrictions anymore). Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1054,8 +1054,7 @@ static void dma_msi_set_affinity(struct spin_lock_irqsave(&iommu->register_lock, flags); dmar_writel(iommu->reg, DMAR_FEDATA_REG, msg.data); - dmar_writel(iommu->reg, DMAR_FEADDR_REG, msg.address_lo); - dmar_writel(iommu->reg, DMAR_FEUADDR_REG, msg.address_hi); + dmar_writeq(iommu->reg, DMAR_FEADDR_REG, msg.address); spin_unlock_irqrestore(&iommu->register_lock, flags); } --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -51,17 +51,10 @@ #define DMAR_IRTA_REG 0xB8 /* intr remap */ #define OFFSET_STRIDE (9) -#define dmar_readl(dmar, reg) readl(dmar + reg) -#define dmar_writel(dmar, reg, val) writel(val, dmar + reg) -#define dmar_readq(dmar, reg) ({ \ - u32 lo, hi; \ - lo = dmar_readl(dmar, reg); \ - hi = dmar_readl(dmar, reg + 4); \ - (((u64) hi) << 32) + lo; }) -#define dmar_writeq(dmar, reg, val) do {\ - dmar_writel(dmar, reg, (u32)val); \ - dmar_writel(dmar, reg + 4, (u32)((u64) val >> 32)); \ - } while (0) +#define dmar_readl(dmar, reg) readl((dmar) + (reg)) +#define dmar_readq(dmar, reg) readq((dmar) + (reg)) +#define dmar_writel(dmar, reg, val) writel(val, (dmar) + (reg)) +#define dmar_writeq(dmar, reg, val) writeq(val, (dmar) + (reg)) #define VER_MAJOR(v) (((v) & 0xf0) >> 4) #define VER_MINOR(v) ((v) & 0x0f) Attachment:
VT-d-MMIO-qword.patch _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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