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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [RFC 2/2] xen/iommu: smmu: Use the p2m IPA size as S2 input-size
From: "Edgar E. Iglesias" <edgar.iglesias@xxxxxxxxxx>
Because we share the p2m tables between SMMU and CPUs,
we need to make sure the SMMU is configured to use the
same S2 input-size as the CPU.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xxxxxxxxxx>
---
xen/drivers/passthrough/arm/smmu.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/xen/drivers/passthrough/arm/smmu.c
b/xen/drivers/passthrough/arm/smmu.c
index 8a9b58b..95e4dce 100644
--- a/xen/drivers/passthrough/arm/smmu.c
+++ b/xen/drivers/passthrough/arm/smmu.c
@@ -1038,6 +1038,7 @@ static void arm_smmu_init_context_bank(struct
arm_smmu_domain *smmu_domain)
struct arm_smmu_device *smmu = smmu_domain->smmu;
void __iomem *cb_base, *gr0_base, *gr1_base;
paddr_t p2maddr;
+ unsigned p2m_ipa_bits;
gr0_base = ARM_SMMU_GR0(smmu);
gr1_base = ARM_SMMU_GR1(smmu);
@@ -1123,6 +1124,14 @@ static void arm_smmu_init_context_bank(struct
arm_smmu_domain *smmu_domain)
/* TTBR0 */
/* Xen: The page table is shared with the P2M code */
ASSERT(smmu_domain->cfg.domain != NULL);
+
+ /* Xen: When building the domain, we need to make sure that the p2m
+ * IPA size is not larger than what SMMUs can handle. It's to late to
+ * do anything about it at this stage, so we simply ASSERT on it.
+ */
+ p2m_ipa_bits = smmu_domain->cfg.domain->arch.p2m.ipa_bits;
+ ASSERT(smmu->s2_input_size >= p2m_ipa_bits);
+
p2maddr = page_to_maddr(smmu_domain->cfg.domain->arch.p2m.root);
dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n",
@@ -1146,7 +1155,10 @@ static void arm_smmu_init_context_bank(struct
arm_smmu_domain *smmu_domain)
reg = TTBCR_TG0_64K;
if (!stage1) {
- reg |= (64 - smmu->s2_input_size) << TTBCR_T0SZ_SHIFT;
+ /* Xen: We reuse the p2m tables, the input size needs
+ * to match the p2m IPA size.
+ */
+ reg |= (64 - p2m_ipa_bits) << TTBCR_T0SZ_SHIFT;
switch (smmu->s2_output_size) {
case 32:
@@ -1795,10 +1807,11 @@ static int arm_smmu_handle_mapping(struct
arm_smmu_domain *smmu_domain,
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
pgd_t *pgd = cfg->pgd;
unsigned long flags;
+ unsigned int p2m_ipa_bits = smmu_domain->cfg.domain->arch.p2m.ipa_bits;
if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
stage = 2;
- input_mask = (1ULL << smmu->s2_input_size) - 1;
+ input_mask = (1ULL << p2m_ipa_bits) - 1;
output_mask = (1ULL << smmu->s2_output_size) - 1;
} else {
stage = 1;
--
1.9.1
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