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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 03/19] xen: arm: call inject_undef_exception directly
Reducing the amount of goto maze considerably.
Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Reviewed-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
xen/arch/arm/traps.c | 56 +++++++++++++++++++++++---------------------------
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 99ceaea..7270116 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -518,13 +518,13 @@ static void inject_iabt64_exception(struct cpu_user_regs
*regs,
#endif
static void inject_undef_exception(struct cpu_user_regs *regs,
- int instr_len)
+ const union hsr hsr)
{
if ( is_32bit_domain(current->domain) )
inject_undef32_exception(regs);
#ifdef CONFIG_ARM_64
else
- inject_undef64_exception(regs, instr_len);
+ inject_undef64_exception(regs, hsr.len);
#endif
}
@@ -1592,11 +1592,11 @@ static void do_cp15_32(struct cpu_user_regs *regs,
case HSR_CPREG32(CNTP_CTL):
case HSR_CPREG32(CNTP_TVAL):
if ( !vtimer_emulate(regs, hsr) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
break;
case HSR_CPREG32(ACTLR):
if ( psr_mode_is_user(regs) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
if ( cp32.read )
*r = v->arch.actlr;
break;
@@ -1612,14 +1612,14 @@ static void do_cp15_32(struct cpu_user_regs *regs,
case HSR_CPREG32(PMUSERENR):
/* RO at EL0. RAZ/WI at EL1 */
if ( psr_mode_is_user(regs) && !hsr.cp32.read )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
goto cp15_32_raz_wi;
case HSR_CPREG32(PMINTENSET):
case HSR_CPREG32(PMINTENCLR):
/* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */
if ( psr_mode_is_user(regs) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
goto cp15_32_raz_wi;
case HSR_CPREG32(PMCR):
case HSR_CPREG32(PMCNTENSET):
@@ -1638,7 +1638,7 @@ static void do_cp15_32(struct cpu_user_regs *regs,
* emulate that register as 0 above.
*/
if ( psr_mode_is_user(regs) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
cp15_32_raz_wi:
if ( cp32.read )
*r = 0;
@@ -1652,8 +1652,7 @@ static void do_cp15_32(struct cpu_user_regs *regs,
cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n",
hsr.bits & HSR_CP32_REGS_MASK);
- undef_cp15_32:
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
return;
}
advance_pc(regs, hsr);
@@ -1673,7 +1672,7 @@ static void do_cp15_64(struct cpu_user_regs *regs,
case HSR_CPREG64(CNTPCT):
case HSR_CPREG64(CNTP_CVAL):
if ( !vtimer_emulate(regs, hsr) )
- goto undef_cp15_64;
+ return inject_undef_exception(regs, hsr);
break;
default:
{
@@ -1685,8 +1684,7 @@ static void do_cp15_64(struct cpu_user_regs *regs,
cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n",
hsr.bits & HSR_CP64_REGS_MASK);
- undef_cp15_64:
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
return;
}
}
@@ -1713,7 +1711,7 @@ static void do_cp14_32(struct cpu_user_regs *regs, const
union hsr hsr)
* is set to 0, which we emulated below.
*/
if ( !cp32.read )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* Implement the minimum requirements:
* - Number of watchpoints: 1
@@ -1731,14 +1729,14 @@ static void do_cp14_32(struct cpu_user_regs *regs,
const union hsr hsr)
* is set to 0, which we emulated below.
*/
if ( !cp32.read )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
*r = 0;
break;
case HSR_CPREG32(DBGDSCREXT):
if ( usr_mode(regs) )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* Implement debug status and control register as RAZ/WI.
* The OS won't use Hardware debug if MDBGen not set
@@ -1756,7 +1754,7 @@ static void do_cp14_32(struct cpu_user_regs *regs, const
union hsr hsr)
case HSR_CPREG32(DBGBCR1):
case HSR_CPREG32(DBGOSDLR):
if ( usr_mode(regs) )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* RAZ/WI */
if ( cp32.read )
*r = 0;
@@ -1764,10 +1762,10 @@ static void do_cp14_32(struct cpu_user_regs *regs,
const union hsr hsr)
case HSR_CPREG32(DBGOSLAR):
if ( usr_mode(regs) )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* WO */
if ( cp32.read )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* else: ignore */
break;
default:
@@ -1777,8 +1775,7 @@ static void do_cp14_32(struct cpu_user_regs *regs, const
union hsr hsr)
cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n",
hsr.bits & HSR_CP32_REGS_MASK);
- undef_cp14_32:
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
return;
}
@@ -1802,7 +1799,7 @@ static void do_cp14_dbg(struct cpu_user_regs *regs, const
union hsr hsr)
gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n",
hsr.bits & HSR_CP64_REGS_MASK);
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
}
static void do_cp(struct cpu_user_regs *regs, const union hsr hsr)
@@ -1817,7 +1814,7 @@ static void do_cp(struct cpu_user_regs *regs, const union
hsr hsr)
ASSERT(!cp.tas); /* We don't trap SIMD instruction */
gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc);
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
}
#ifdef CONFIG_ARM_64
@@ -1847,7 +1844,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
* undef.
*/
if ( psr_mode_is_user(regs) )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
goto sysreg_raz_wi;
case HSR_SYSREG_MDCCSR_EL0:
@@ -1856,7 +1853,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
* register as RAZ/WI above. So RO at both EL0 and EL1.
*/
if ( !hsr.sysreg.read )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
*x = 0;
break;
@@ -1865,7 +1862,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
case HSR_SYSREG_PMUSERENR_EL0:
/* RO at EL0. RAZ/WI at EL1 */
if ( psr_mode_is_user(regs) && !hsr.sysreg.read )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
goto sysreg_raz_wi;
case HSR_SYSREG_PMCR_EL0:
case HSR_SYSREG_PMCNTENSET_EL0:
@@ -1884,7 +1881,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
* emulate that register as 0 above.
*/
if ( psr_mode_is_user(regs) )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
sysreg_raz_wi:
if ( hsr.sysreg.read )
*x = 0;
@@ -1894,14 +1891,14 @@ static void do_sysreg(struct cpu_user_regs *regs,
/* Write only, Write ignore registers: */
case HSR_SYSREG_OSLAR_EL1:
if ( hsr.sysreg.read )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
/* else: write ignored */
break;
case HSR_SYSREG_CNTP_CTL_EL0:
case HSR_SYSREG_CNTP_TVAL_EL0:
case HSR_SYSREG_CNTP_CVAL_EL0:
if ( !vtimer_emulate(regs, hsr) )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
break;
case HSR_SYSREG_ICC_SGI1R_EL1:
if ( !vgic_emulate(regs, hsr) )
@@ -1931,8 +1928,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
sysreg.reg, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n",
hsr.bits & HSR_SYSREG_REGS_MASK);
- undef_sysreg:
- inject_undef_exception(regs, hsr.sysreg.len);
+ inject_undef_exception(regs, hsr);
return;
}
}
--
1.7.10.4
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