Re: [Xen-devel] [PATCH v15 09/15] pvqspinlock: Implement simple paravirt support for the qspinlock

[Waiman Long <waiman.long@xxxxxx>]

On 04/13/2015 11:09 AM, Peter Zijlstra wrote:
> On Thu, Apr 09, 2015 at 05:41:44PM -0400, Waiman Long wrote:
> > > > +__visible void __pv_queue_spin_unlock(struct qspinlock *lock)
> > > > +{
> > > > +       struct __qspinlock *l = (void *)lock;
> > > > +       struct pv_node *node;
> > > > +
> > > > +       if (likely(cmpxchg(&l->locked, _Q_LOCKED_VAL, 0) == _Q_LOCKED_VAL))
> > > > +               return;
> > > > +
> > > > +       /*
> > > > +        * The queue head has been halted. Need to locate it and wake it up.
> > > > +        */
> > > > +       node = pv_hash_find(lock);
> > > > +       smp_store_release(&l->locked, 0);
> > > Ah yes, clever that.
> > >
> > > > +       /*
> > > > +        * At this point the memory pointed at by lock can be freed/reused,
> > > > +        * however we can still use the PV node to kick the CPU.
> > > > +        */
> > > > +       if (READ_ONCE(node->state) == vcpu_halted)
> > > > +               pv_kick(node->cpu);
> > > > +}
> > > > +PV_CALLEE_SAVE_REGS_THUNK(__pv_queue_spin_unlock);
> > > However I feel the PV_CALLEE_SAVE_REGS_THUNK thing belongs in the x86
> > > code.
> > That is why I originally put my version of the qspinlock_paravirt.h header
> > file under arch/x86/include/asm. Maybe we should move it back there. Putting
> > the thunk in arch/x86/kernel/kvm.c didn't work when you consider that the
> > Xen code also need that.
> Well the function is 'generic' and belong here I think. Its just the
> PV_CALLEE_SAVE_REGS_THUNK thing that arch specific. Should have live in
> arch/x86/kernel/paravirt-spinlocks.c instead?
Another alternative is to put the PV_CALLEE_SAVE_REGS_THUNK into a 
separate asm/qspinlock_paravirt.h file and included in the generic 
qspinlock_paravirt.h file. By putting the thunk with the 
__pv_queue_spin_unlock together in the same file, we can make the thunk 
and the unlock fast path (_Q_SLOW_VAL not set) go into two adjacent 
instruction cachelines. I think that may help a bit in term of performance.
Cheers,
Longman


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