[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 08/19] xen: arm: implement handling of ACTLR_EL1 trap
Hi Ian, On 31/03/2015 12:07, Ian Campbell wrote: While annotating ACTLR I noticed that we don't appear to handle the 64-bit version of this trap. Do so and annotate everything. While Linux doesn't use ACTLR_EL1 on aarch64, another OS may use it.I'm not sure if we should consider it as a possible security issue as at least the Cortex A53 implements the register RES0. Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx> --- xen/arch/arm/traps.c | 20 ++++++++++++++++++++ xen/include/asm-arm/sysregs.h | 1 + 2 files changed, 21 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 70e1b4d..ca43f79 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1647,6 +1647,13 @@ static void do_cp15_32(struct cpu_user_regs *regs, if ( !vtimer_emulate(regs, hsr) ) return inject_undef_exception(regs, hsr); break; + + /* + * HSR_EL2.TASC / HSR.TAC I don't find any TASC in the ARMv8 doc. Did you intend to say TACR? Also it's not HSR but HCR. + * + * ARMv7 (DDI 0406C.b): B1.14.6 + * ARMv8 (DDI 0487A.d): G6.2.1 + */ case HSR_CPREG32(ACTLR): if ( psr_mode_is_user(regs) ) return inject_undef_exception(regs, hsr); @@ -1849,9 +1856,22 @@ static void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { register_t *x = select_user_reg(regs, hsr.sysreg.reg); + struct vcpu *v = current; switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) { + /* + * HSR_EL2.TASC Same question here for TASC. Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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