Re: [Xen-devel] [PATCH v3] docs: add PVH specification

[Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>]

> >> +`CR0` has the following bits set by Xen:
> >> +
> >> +  * PE (bit 0): protected mode enable.
> >> +  * ET (bit 4): 387 or newer processor.
> >> +  * PG (bit 31): paging enabled.
> > 
> > Also TS (at least that is what the Linux code says:
> > 
> > /* Some of these are setup in 'secondary_startup_64'. The others:       
> > * X86_CR0_TS, X86_CR0_PE, X86_CR0_ET are set by Xen for HVM guests     
> > * (which PVH shared codepaths), while X86_CR0_PG is for PVH. */        
> > 
> > Perhaps it is incorrect?
> 
> I think this comment is outdated/incorrect. This is the CR0 value I see 
> on a FreeBSD PVH start-of-day:
> 
> 0x80000011 (PE, ET and PG bits set)
> 

Reading the code I see

construct_vmcs
        hvm_update_guest_cr(v, 0);
                vmx_update_guest_cr

Then this code:
        1234         if ( !(v->arch.hvm_vcpu.guest_cr[0] & X86_CR0_TS) )        
             
        1235         {                                                          
             
        1236             if ( v != current )                                    
             
        1237                 hw_cr0_mask |= X86_CR0_TS;                         
             

        ...
        1279         v->arch.hvm_vcpu.hw_cr[0] =                                
             
        1280             v->arch.hvm_vcpu.guest_cr[0] | hw_cr0_mask;            
             
        1281         __vmwrite(GUEST_CR0, v->arch.hvm_vcpu.hw_cr[0]);           
             

Same logic on the AMD side, albeit less complicated.

But this is Monday morning so I must be missing something
as your values don't match with this.


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