Re: [Xen-devel] [PATCH v9 3/7] xen/arm: Add support for GIC v3

[Vijay Kilari <vijay.kilari@xxxxxxxxx>]

On Mon, Sep 8, 2014 at 3:12 PM, Ian Campbell <Ian.Campbell@xxxxxxxxxx> wrote:
> On Fri, 2014-09-05 at 01:27 +0100, Stefano Stabellini wrote:
>> On Thu, 4 Sep 2014, vijay.kilari@xxxxxxxxx wrote:
>> > From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>> >
>> > Add support for GIC v3 specification System register access(SRE)
>> > is enabled to access cpu and virtual interface registers based
>> > on kernel GICv3 driver.
>> >
>> > This patch adds only basic v3 support.
>> > Does not support Interrupt Translation support (ITS)
>> >
>> > Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>>
>> [...]
>>
>> > +static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t 
>> > *mask)
>> > +{
>> > +    unsigned int cpu;
>> > +    uint64_t affinity;
>> > +
>> > +    ASSERT(!cpumask_empty(mask));
>> > +
>> > +    spin_lock(&gicv3.lock);
>> > +
>> > +    cpu = gicv3_get_cpu_from_mask(mask);
>> > +    affinity = gicv3_mpidr_to_affinity(cpu);
>> > +    /* Make sure we don't broadcast the interrupt */
>> > +    affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
>>
>> I would like an ASSERT(affinity != 0);

affinity 0 is also valid value for cpu0

>
> Should the v2 code do the same then?
>
> There is no way that this value can be controlled by the guest then?
>
>>
>> Other than that:
>>
>> Acked-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
>>
>
>

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