Re: [Xen-devel] [PATCH v6 3/4] x86/mem_event: Deliver gla fault EPT violation information

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 11.08.14 at 16:48, <tamas.lengyel@xxxxxxxxxxxx> wrote:
> On Intel EPT the exit qualification generated by a violation also includes a 
> bit (EPT_GLA_FAULT) which describes the following information:
> Set if the access causing the EPT violation is to a guest-physical address 
> that is the translation of a linear address. Clear if the access causing the 
> EPT violation is to a paging-structure entry as part of a page walk or the 
> update of an accessed or dirty bit.
> 
> For more information see Table 27-7 in the Intel SDM.
> 
> This patch extends the mem_event system to deliver this extra information, 
> which could be useful for determining the cause of a violation.
> 
> v6: Fixes regarding the enum usage.
> v5: Add missing bits to the SVM side, style fixes and switching to shared 
> struct+enum in mm.h.
> v4: Use new bitmaps to pass information.
> v3: Style fixes.
> v2: Split gla_fault into fault_in_gpt and fault_gla to be more compatible 
> with the AMD implementation.
> 
> Signed-off-by: Tamas K Lengyel <tamas.lengyel@xxxxxxxxxxxx>

Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>

albeit if I'll be the one to commit this I'm likely to change ...

> --- a/xen/include/asm-x86/hvm/svm/svm.h
> +++ b/xen/include/asm-x86/hvm/svm/svm.h
> @@ -105,4 +105,10 @@ extern u32 svm_feature_flags;
>  extern void svm_host_osvw_reset(void);
>  extern void svm_host_osvw_init(void);
>  
> +/* EXITINFO1 fields on NPT faults */
> +#define _NPT_PFEC_FAULT_WITH_GLA     32
> +#define NPT_PFEC_FAULT_WITH_GLA      (1UL<<_NPT_PFEC_FAULT_WITH_GLA)
> +#define _NPT_PFEC_FAULT_IN_GPT       33
> +#define NPT_PFEC_FAULT_IN_GPT        (1UL<<_NPT_PFEC_FAULT_IN_GPT)

... these to get rid of the FAULT_ and convert the non-prefix
portion of them to lower case, matching the PFEC_ ones.

Jan


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