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Re: [Xen-devel] [PATCH] x86/HVM: extend LAPIC shortcuts around P2M lookups

>>> On 06.08.14 at 11:38, <tim@xxxxxxx> wrote:
> At 09:34 +0100 on 06 Aug (1407314042), Jan Beulich wrote:
>> >>> On 05.08.14 at 21:53, <tim@xxxxxxx> wrote:
>> > I'd be extremely uncomfortable with anything like tis unless there's a
>> > way to get either the ifetch buffer or a partial decode out of the CPU
>> > (which IIRC can't be done on x86 though it can on ARM).
>> On NPT we also get the instruction bytes on nested page faults, at
>> least on newer hardware. So maybe we could cook up something
>> along the lines you indicate by flagging that the instruction bytes
>> came from hardware.
> Oh good -- yes, both of those approaches sound very encouraging.

Actually after some more thinking I concluded that on NPT we can't
go the outlined route: We can't distinguish primary memory accesses
from implicit ones (descriptor tables, TSS I/O permission bit map), and
hence can't deduce from just the instruction bytes having come from
hardware that a certain GPA can be used without first translating the

Anyway, the performance effect of the changes we have so far
seem to help the AMD side enough to now perform better than the
Intel variant, despite the (not yet formally posted) EPT related
patch obviously not possibly having any positive effect (and it is
for the reason of wanting to be really certain that I'm not
introducing a regression making things appear to perform better
that I still didn't post that final patch; of course the conflict with
Tamas's work also makes it less than ideal to post right now).


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