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Re: [Xen-devel] [PATCH v2 1/3] xen/arm: Add 4-level page table for stage 2 translation

On Wed, 2014-07-16 at 17:12 +0530, Vijay Kilari wrote:
> On Tue, Jul 15, 2014 at 7:17 PM, Ian Campbell <Ian.Campbell@xxxxxxxxxx> wrote:
> > On Tue, 2014-05-27 at 12:16 +0530, vijay.kilari@xxxxxxxxx wrote:
> >> From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
> >>
> >> To support 48-bit Physical Address support, add 4-level
> >> page tables for stage 2 translation.
> >> With this patch stage 1 and stage 2 translation at EL2 are
> >> with 4-levels
> >
> > I've been playing with this patch on various platforms and unfortunately
> > there is a rather large snag here, AFAICT. Which is that 4-level stage 2
> > pages are only available when ID_AA64MMFR0_EL1.PARange >= 44 bits, see
> > table D4-5 in the ARMv8 ARM.
>  I read from "Table D5-18 Properties of the address lookup levels, 4KB
> granule size"
> Where the lookup level and granule size details are provided. For
> above 39 bit PA
> zero level is used.

This is D4-19 in my copy -- OOI which version of the ARM are you working
from? Mine is ARM DDI0487A.B.

> IMO, conversion above 40 bits, 4 levels are required. However if we use
> concatenation, conversion can be managed with 3 levels.
> Please see "Figure D5-8 General view of VMSAv8-64 stage 2 address translation,
> 4KB granule".
> I think Xen is using concatenation method to handle 40 bits conversion.

Correct, but that doesn't scale to 48bits, 3-levels maxs out at 16
concatenated first level tables allowing for 42 bit addressing.

So the upshot is that to support both 40- and 48-bit systems we must
dynamically support 4-level and 3-level (concatenated) tables.

> our platform has peripherals placed above 2^40 limit. where I could
> access with 48-bit support patch series

OK. Thanks.


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