[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v7 4/5] xen/arm: add SGI handling for GICv3
Hi Vijay, On 07/11/2014 01:51 PM, vijay.kilari@xxxxxxxxx wrote: > From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx> > > In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2. > Handle the trap and inject SGI to vcpu. > > Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx> > --- > v7: - Introduced callback for sysreg emulation > - Removed unused parameter in inject_undef_exception() > - Use inject_undef64_exception for reporting sysreg > handling failure > > v6: - Removed forward declaration of vgic_to_sgi() in vgic-v3.c > - Used vgic callback for SGI handling > - Alignment changes > --- > xen/arch/arm/traps.c | 15 +++++++++++ > xen/arch/arm/vgic-v3.c | 52 > +++++++++++++++++++++++++++++++++++++ > xen/arch/arm/vgic.c | 7 +++++ > xen/include/asm-arm/gic_v3_defs.h | 7 +++++ > xen/include/asm-arm/sysregs.h | 3 +++ > xen/include/asm-arm/vgic.h | 3 +++ > 6 files changed, 87 insertions(+) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index 686d8b7..775bef1 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -41,6 +41,7 @@ > #include "decode.h" > #include "vtimer.h" > #include <asm/gic.h> > +#include <asm/vgic.h> > > /* The base of the stack must always be double-word aligned, which means > * that both the kernel half of struct cpu_user_regs (which is pushed in > @@ -1641,6 +1642,20 @@ static void do_sysreg(struct cpu_user_regs *regs, > domain_crash_synchronous(); > } > break; > + case HSR_SYSREG_ICC_SGI1R_EL1: > + if ( !vgic_emulate(regs, hsr) ) > + { > + dprintk(XENLOG_WARNING, > + "failed emulation of sysreg ICC_SGI1R_EL1 access\n"); > + inject_undef64_exception(regs, hsr.len); > + } > + break; > + case HSR_SYSREG_ICC_SGI0R_EL1: > + case HSR_SYSREG_ICC_ASGI1R_EL1: > + /* TBD: Implement to support secure grp0/1 SGI forwarding */ > + dprintk(XENLOG_WARNING, > + "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not > supported\n"); > + inject_undef64_exception(regs, hsr.len); > default: > bad_sysreg: > { > diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c > index 2bf0e7c..feee486 100644 > --- a/xen/arch/arm/vgic-v3.c > +++ b/xen/arch/arm/vgic-v3.c > @@ -834,6 +834,57 @@ write_ignore_64: > return 1; > } > > +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir) > +{ > + int virq; > + int irqmode; > + enum gic_sgi_mode sgi_mode; > + unsigned long vcpu_mask = 0; > + > + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK; > + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK; > + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK; > + > + /* Map GIC sgi value to enum value */ > + switch ( irqmode ) > + { > + case ICH_SGI_TARGET_LIST: > + sgi_mode = SGI_TARGET_LIST; > + break; > + case ICH_SGI_TARGET_OTHERS: > + sgi_mode = SGI_TARGET_OTHERS; > + break; > + default: > + BUG(); > + } > + > + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask); > +} > + > +static int vgicv3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) > +{ > + struct vcpu *v = current; > + struct hsr_sysreg sysreg = hsr.sysreg; > + register_t *r = select_user_reg(regs, sysreg.reg); > + > + ASSERT (hsr.ec == HSR_EC_SYSREG); > + > + switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) > + { > + case HSR_SYSREG_ICC_SGI1R_EL1: > + /* WO */ > + if ( !sysreg.read ) > + return vgicv3_to_sgi(v, *r); > + else > + { > + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n"); > + return 0; > + } > + default: > + return 0; > + } > +} > + > static const struct mmio_handler_ops vgic_rdistr_mmio_handler = { > .read_handler = vgic_v3_rdistr_mmio_read, > .write_handler = vgic_v3_rdistr_mmio_write, > @@ -884,6 +935,7 @@ static int vgicv3_domain_init(struct domain *d) > static const struct vgic_ops v3_ops = { > .vcpu_init = vgicv3_vcpu_init, > .domain_init = vgicv3_domain_init, > + .emulate_sysreg = vgicv3_emulate_sysreg, > }; > > int vgic_v3_init(struct domain *d) > diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c > index 3647497..e15d509 100644 > --- a/xen/arch/arm/vgic.c > +++ b/xen/arch/arm/vgic.c > @@ -343,6 +343,13 @@ out: > smp_send_event_check_mask(cpumask_of(v->processor)); > } > > +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) > +{ > + struct vcpu *v = current; > + > + return v->domain->arch.vgic.handler->emulate_sysreg(regs, hsr); > +} > + You didn't implement emulate_sysreg for vgic-v2. If the GICv3 is misprogrammed, Xen will segfault... Please either implement emulate_sysreg on vgic-v2 by return 1 or check that the function is not NULL. Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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