Re: [Xen-devel] [PATCH v6 4/5] xen/arm: add SGI handling for GICv3

[Vijay Kilari <vijay.kilari@xxxxxxxxx>]

On Thu, Jul 3, 2014 at 8:03 PM, Julien Grall <julien.grall@xxxxxxxxxx> wrote:
> Hi Vijay,
>
> On 07/03/2014 09:37 AM, vijay.kilari@xxxxxxxxx wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>>
>> In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
>> Handle the trap and inject SGI to vcpu.
>>
>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>> ---
>>  xen/arch/arm/traps.c              |   30 +++++++++++++++++
>>  xen/arch/arm/vgic-v3.c            |   65 
>> +++++++++++++++++++++++++++++++++----
>>  xen/include/asm-arm/gic_v3_defs.h |    7 ++++
>>  xen/include/asm-arm/sysregs.h     |    3 ++
>>  xen/include/asm-arm/vgic.h        |    1 +
>>  5 files changed, 100 insertions(+), 6 deletions(-)
>>
>>  struct reg_ctxt {
>>      /* Guest-side state */
>>      uint32_t sctlr_el1;
>> @@ -1591,6 +1604,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
>>                        union hsr hsr)
>>  {
>>      register_t *x = select_user_reg(regs, hsr.sysreg.reg);
>> +    register_t addr;
>>
>>      switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
>>      {
>> @@ -1641,6 +1655,22 @@ static void do_sysreg(struct cpu_user_regs *regs,
>>              domain_crash_synchronous();
>>          }
>>          break;
>> +    case HSR_SYSREG_ICC_SGI1R_EL1:
>> +        if ( !vgic_emulate(regs, hsr) )
>> +        {
>> +            addr = READ_SYSREG64(FAR_EL2);
>> +            dprintk(XENLOG_WARNING,
>> +                    "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
>> +            inject_undef_exception(regs, addr, hsr.len);
>
> AFAIK, sysreg only exist for 64 bits guest. At least the precondition to
> call this function is the guest is 64 bits (see the caller). So you can
> use directly inject_undef64_exception.

What if the Guest is running int Aarch32 bit mode and make
sysreg access?

Regards
Vijay

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