[Xen-devel] [PATCH v9a 2/6] xen/arm: move pending_irq structure to vgic header file

[vijay.kilari@xxxxxxxxx]

From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>

gic.h requires definition of pending_irq structure defined
in domain.h and domain.h requires gic_state structure defined
in gic.h and hence there is inter-dependency between domain.h
and gic.h files.

So move pending_irq to vgic.h which is relevant place for this
structure and break domain.h and gic.h interdependency

By this move irq_to_pending function declaration from gic.h
to vgic.h

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/include/asm-arm/domain.h |   57 -----------------------------------------
 xen/include/asm-arm/gic.h    |    2 +-
 xen/include/asm-arm/vgic.h   |   58 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 077ac1e..2a1e976 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -13,63 +13,6 @@
 #include <xen/serial.h>
 #include <xen/hvm/iommu.h>
 
-struct pending_irq
-{
-    /*
-     * The following two states track the lifecycle of the guest irq.
-     * However because we are not sure and we don't want to track
-     * whether an irq added to an LR register is PENDING or ACTIVE, the
-     * following states are just an approximation.
-     *
-     * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for
-     * injection into the guest's LRs.
-     *
-     * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register,
-     * therefore the guest is aware of it. From the guest point of view
-     * the irq can be pending (if the guest has not acked the irq yet)
-     * or active (after acking the irq).
-     *
-     * In order for the state machine to be fully accurate, for level
-     * interrupts, we should keep the interrupt's pending state until
-     * the guest deactivates the irq. However because we are not sure
-     * when that happens, we instead track whether there is an interrupt
-     * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to
-     * an LR register. We set it when we receive another interrupt
-     * notification.  Therefore it is possible to set
-     * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We
-     * could also change the state of the guest irq in the LR register
-     * from active to active and pending, but for simplicity we simply
-     * inject a second irq after the guest EOIs the first one.
-     *
-     *
-     * An additional state is used to keep track of whether the guest
-     * irq is enabled at the vgicd level:
-     *
-     * GIC_IRQ_GUEST_ENABLED: the guest IRQ is enabled at the VGICD
-     * level (GICD_ICENABLER/GICD_ISENABLER).
-     *
-     */
-#define GIC_IRQ_GUEST_QUEUED   0
-#define GIC_IRQ_GUEST_ACTIVE   1
-#define GIC_IRQ_GUEST_VISIBLE  2
-#define GIC_IRQ_GUEST_ENABLED  3
-    unsigned long status;
-    struct irq_desc *desc; /* only set it the irq corresponds to a physical 
irq */
-    int irq;
-#define GIC_INVALID_LR         ~(uint8_t)0
-    uint8_t lr;
-    uint8_t priority;
-    /* inflight is used to append instances of pending_irq to
-     * vgic.inflight_irqs */
-    struct list_head inflight;
-    /* lr_queue is used to append instances of pending_irq to
-     * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue
-     * accesses are protected with the vgic lock.
-     * TODO: when implementing irq migration, taking only the current
-     * vgic lock is not going to be enough. */
-    struct list_head lr_queue;
-};
-
 struct hvm_domain
 {
     uint64_t              params[HVM_NR_PARAMS];
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index ed610cb..875729e 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -143,6 +143,7 @@
 #ifndef __ASSEMBLY__
 #include <xen/device_tree.h>
 #include <xen/irq.h>
+#include <asm-arm/vgic.h>
 
 #define DT_COMPAT_GIC_CORTEX_A15     "arm,cortex-a15-gic"
 #define DT_COMPAT_GIC_CORTEX_A7      "arm,cortex-a7-gic"
@@ -188,7 +189,6 @@ enum gic_version {
 };
 
 extern enum gic_version gic_hw_version(void);
-extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
 
 /* Program the GIC to route an interrupt */
 extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t 
*cpu_mask,
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 92f1e86..003c3e9 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -20,6 +20,63 @@
 
 #include <xen/bitops.h>
 
+struct pending_irq
+{
+    /*
+     * The following two states track the lifecycle of the guest irq.
+     * However because we are not sure and we don't want to track
+     * whether an irq added to an LR register is PENDING or ACTIVE, the
+     * following states are just an approximation.
+     *
+     * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for
+     * injection into the guest's LRs.
+     *
+     * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register,
+     * therefore the guest is aware of it. From the guest point of view
+     * the irq can be pending (if the guest has not acked the irq yet)
+     * or active (after acking the irq).
+     *
+     * In order for the state machine to be fully accurate, for level
+     * interrupts, we should keep the interrupt's pending state until
+     * the guest deactivates the irq. However because we are not sure
+     * when that happens, we instead track whether there is an interrupt
+     * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to
+     * an LR register. We set it when we receive another interrupt
+     * notification.  Therefore it is possible to set
+     * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We
+     * could also change the state of the guest irq in the LR register
+     * from active to active and pending, but for simplicity we simply
+     * inject a second irq after the guest EOIs the first one.
+     *
+     *
+     * An additional state is used to keep track of whether the guest
+     * irq is enabled at the vgicd level:
+     *
+     * GIC_IRQ_GUEST_ENABLED: the guest IRQ is enabled at the VGICD
+     * level (GICD_ICENABLER/GICD_ISENABLER).
+     *
+     */
+#define GIC_IRQ_GUEST_QUEUED   0
+#define GIC_IRQ_GUEST_ACTIVE   1
+#define GIC_IRQ_GUEST_VISIBLE  2
+#define GIC_IRQ_GUEST_ENABLED  3
+    unsigned long status;
+    struct irq_desc *desc; /* only set it the irq corresponds to a physical 
irq */
+    int irq;
+#define GIC_INVALID_LR         ~(uint8_t)0
+    uint8_t lr;
+    uint8_t priority;
+    /* inflight is used to append instances of pending_irq to
+     * vgic.inflight_irqs */
+    struct list_head inflight;
+    /* lr_queue is used to append instances of pending_irq to
+     * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue
+     * accesses are protected with the vgic lock.
+     * TODO: when implementing irq migration, taking only the current
+     * vgic lock is not going to be enough. */
+    struct list_head lr_queue;
+};
+
 /* Represents state corresponding to a block of 32 interrupts */
 struct vgic_irq_rank {
     spinlock_t lock; /* Covers access to all other members of this struct */
@@ -87,6 +144,7 @@ extern void domain_vgic_free(struct domain *d);
 extern int vcpu_vgic_init(struct vcpu *v);
 extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
 extern void vgic_clear_pending_irqs(struct vcpu *v);
+extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
 
 extern int vcpu_vgic_free(struct vcpu *v);
 #endif /* __ASM_ARM_VGIC_H__ */
-- 
1.7.9.5


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