[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v7 3/6] xen/arm: inflight irqs during migration
On 07/03/2014 05:53 PM, Stefano Stabellini wrote: > static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) > { > const unsigned long mask = r; > @@ -598,35 +638,60 @@ static int vgic_distr_mmio_write(struct vcpu *v, > mmio_info_t *info) > goto write_ignore; > > case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN: > + { > + /* unsigned long needed for find_next_bit */ > + unsigned long target; > + int i; > if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width; > rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR); > if ( rank == NULL) goto write_ignore; > /* 8-bit vcpu mask for this domain */ > BUG_ON(v->domain->max_vcpus > 8); > - tr = (1 << v->domain->max_vcpus) - 1; > + target = (1 << v->domain->max_vcpus) - 1; > if ( dabt.size == 2 ) > - tr = tr | (tr << 8) | (tr << 16) | (tr << 24); > + target = target | (target << 8) | (target << 16) | (target << > 24); > else > - tr = (tr << (8 * (offset & 0x3))); > - tr &= *r; > + target = (target << (8 * (offset & 0x3))); > + target &= *r; > /* ignore zero writes */ > - if ( !tr ) > + if ( !target ) > goto write_ignore; > /* For word reads ignore writes where any single byte is zero */ > if ( dabt.size == 2 && > - !((tr & 0xff) && (tr & (0xff << 8)) && > - (tr & (0xff << 16)) && (tr & (0xff << 24)))) > + !((target & 0xff) && (target & (0xff << 8)) && > + (target & (0xff << 16)) && (target & (0xff << 24)))) > goto write_ignore; > vgic_lock_rank(v, rank); > + i = 0; > + while ( (i = find_next_bit(&target, 32, i)) < 32 ) > + { > + unsigned int irq, target, old_target; target is already defined above, and this will shadow this previous definition. I would rename one of them to avoid coding error later. -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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