[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Xen-devel] ARM Generic Timer interrupt

Hello, all.

I am trying to run QNX as domU under XEN (4.4.0) on OMAP5 platform (ARM32).
For this purposes I have made some changes to origin TI OMAP5 BSP.
Also I have created QNX IFS loader for Xen domain builder.

Currently, dom0 (Linux Kernel) loads QNX as domU. The QNX boots without crashes,
and I have console (I left only one hw block in QNX - UART,
I need it for debug output while HVC is not implemented).

During bringing up I have encountered with next problem.
1. QNX (our BSP) uses ARM Generic Timer as system timer:
QNX doesn't mask/unmask timer interrupt. Of course the QNX doesn't know that interrupt mask may be set by someone else
and that it should be reset for timer interrupt to occur again.

2. XEN handles the firing ARM Generic Timer:
Before injecting irq to the guest the XEN sets interrupt mask for the virtual timer.


static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
ÂÂÂ current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0);
ÂÂÂ WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL0);
ÂÂÂ vgic_vcpu_inject_irq(current, current->arch.virt_timer.irq, 1);

And as result of run under XEN we don't have timer interrupts in QNX.
I have changed interrupt handler in QNX to unmask timer interrupt before return.
But, I have question:
Should the Hypervisor masks virtual timer IRQ on his own?
It is a guest's resource and the guest itself should decide what to do.
For example, I see that Linux Kernel (3.8) sets and clears timer interrupt mask by itself.

Thank you.


Oleksandr Tyshchenko | Embedded Dev
Xen-devel mailing list



Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.