x86/HAP: also flush TLB when altering a present 1G entry

I actually wonder whether it is really correct to avoid the flush when
updating intermediate page table entries.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/mm/hap/hap.c
+++ b/xen/arch/x86/mm/hap/hap.c
@@ -712,7 +712,7 @@ hap_write_p2m_entry(struct vcpu *v, unsi
 
     safe_write_pte(p, new);
     if ( (old_flags & _PAGE_PRESENT)
-         && (level == 1 || (level == 2 && (old_flags & _PAGE_PSE))) )
+         && (level == 1 || (old_flags & _PAGE_PSE)) )
              flush_tlb_mask(d->domain_dirty_cpumask);
 
     paging_unlock(d);