Re: [Xen-devel] [PATCH v2 2/3] x86/AMD: support further feature masking MSRs

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 07.04.14 at 17:21, <boris.ostrovsky@xxxxxxxxxx> wrote:
> On 04/07/2014 05:43 AM, Jan Beulich wrote:
> 
> @@ -179,11 +196,39 @@ static void __devinit set_cpuidmask(cons
>       printk("Writing CPUID extended feature mask ECX:EDX -> %08Xh:%08Xh\n",
>              extfeat_ecx, extfeat_edx);
>   
> +     if (c->cpuid_level >= 7)
> +             cpuid_count(7, 0, &eax, &ebx, &ecx, &edx);
> +     else
> +             ebx = eax = 0;
> +     if ((eax | ebx) && ~(l7s0_eax & l7s0_ebx)) {
> +             if (l7s0_eax > eax)
> +                     l7s0_eax = eax;
> +             l7s0_ebx &= ebx;
> 
> 
> Can you explain why eax is treated differently here (i.e. not ANDing it 
> as is done with ebx)?

Generally I think code like this implies that you know the specification:
eax here represents the maximum supported subleaf, and hence
needs to be limited rather than masked.

Jan


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