Re: [Xen-devel] [PATCH v1 1/2] X86: expose RDSEED, ADX, and PREFETCHW to pv/hvm

["Wu, Feng" <feng.wu@xxxxxxxxx>]

> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxx
> [mailto:xen-devel-bounces@xxxxxxxxxxxxx] On Behalf Of Liu, Jinsong
> Sent: Sunday, February 16, 2014 10:59 PM
> To: Ian.Campbell@xxxxxxxxxx; xen-devel@xxxxxxxxxxxxx
> Cc: haoxudong.hao@xxxxxxxxx; Jan Beulich
> Subject: [Xen-devel] [PATCH v1 1/2] X86: expose RDSEED, ADX, and
> PREFETCHW to pv/hvm
> 
> From 2fe617b6e7350ee1d635b0365914aa0d31f4fadd Mon Sep 17 00:00:00
> 2001
> From: Liu Jinsong <jinsong.liu@xxxxxxxxx>
> Date: Thu, 13 Feb 2014 21:05:01 +0800
> Subject: [PATCH 1/2] X86: expose RDSEED, ADX, and PREFETCHW to pv/hvm
> 
> Intel recently release some new features, including RDSEED, ADX, and
> PREFETCHW.
> This patch expose these new features to pv and hvm.
> 
> Signed-off-by: Xudong Hao <xudong.hao@xxxxxxxxx>
> Signed-off-by: Liu Jinsong <jinsong.liu@xxxxxxxxx>
> ---
>  tools/libxc/xc_cpufeature.h |    3 +++
>  tools/libxc/xc_cpuid_x86.c  |    5 +++++
>  2 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
> index c464e3a..09b2c82 100644
> --- a/tools/libxc/xc_cpufeature.h
> +++ b/tools/libxc/xc_cpufeature.h
> @@ -137,5 +137,8 @@
>  #define X86_FEATURE_ERMS         9 /* Enhanced REP MOVSB/STOSB */
>  #define X86_FEATURE_INVPCID     10 /* Invalidate Process Context ID */
>  #define X86_FEATURE_RTM         11 /* Restricted Transactional Memory
> */
> +#define X86_FEATURE_RDSEED      18 /* RDSEED instruction */
> +#define X86_FEATURE_ADX         19 /* ADCX, ADOX instructions */
> +
> 
>  #endif /* __LIBXC_CPUFEATURE_H */
> diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
> index bbbf9b8..9264039 100644
> --- a/tools/libxc/xc_cpuid_x86.c
> +++ b/tools/libxc/xc_cpuid_x86.c
> @@ -197,6 +197,7 @@ static void intel_xc_cpuid_policy(
> 
>          /* Only a few features are advertised in Intel's 0x80000001. */
>          regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
> +
> bitmaskof(X86_FEATURE_3DNOWPREFETCH) |
>                                 bitmaskof(X86_FEATURE_ABM);
>          regs[3] &= ((is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
>                      (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
> @@ -371,6 +372,8 @@ static void xc_cpuid_hvm_policy(
>                          bitmaskof(X86_FEATURE_ERMS) |
>                          bitmaskof(X86_FEATURE_INVPCID) |
>                          bitmaskof(X86_FEATURE_RTM)  |
> +                        bitmaskof(X86_FEATURE_RDSEED)  |
> +                        bitmaskof(X86_FEATURE_ADX)  |
>                          bitmaskof(X86_FEATURE_FSGSBASE));
>          } else
>              regs[1] = 0;
> @@ -502,6 +505,8 @@ static void xc_cpuid_pv_policy(
>                          bitmaskof(X86_FEATURE_BMI2) |
>                          bitmaskof(X86_FEATURE_ERMS) |
>                          bitmaskof(X86_FEATURE_RTM)  |
> +                        bitmaskof(X86_FEATURE_RDSEED)  |
> +                        bitmaskof(X86_FEATURE_ADX)  |
>                          bitmaskof(X86_FEATURE_FSGSBASE));
>          else
>              regs[1] = 0;
> --
> 1.7.1
> 

I tested this patchset on Intel new CPU, it works fine. Seems the changes for
the tools is not in the upstream while the changes for Xen itself has been
upstreamed. Could you please take a look at this, Ian? Thanks a lot!

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Thanks,
Feng

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