[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH v4 5/6] xen: arm: relax barriers in tlb flushes
On 04/03/2014 01:18 PM, Ian Campbell wrote: > On Thu, 2014-04-03 at 12:12 +0100, Julien Grall wrote: >> On 04/03/2014 09:59 AM, Ian Campbell wrote: >>> @@ -333,12 +333,12 @@ static inline void >>> flush_xen_data_tlb_range_va(unsigned long va, >>> unsigned long size) >>> { >>> unsigned long end = va + size; >>> - dsb(sy); /* Ensure preceding are visible */ >>> + dsb(ish); /* Ensure preceding are visible */ >> >> I'm a bit lost with ish/nsh/sy/... shall we keep sy here? >> flush_xen_data_tlb is used in iounmap > > Is it? I can't see it. I do see it in clear_fixmap though. Sorry I though it was used by create_xen_entries... that made me think, create_xen_entries should use flush_xen_data_tlb_range_va as the mapping is common with the other CPUs. >> and we want to make sure that >> every write as been done just before. > > The barrier here is to ensure that any writes to the page tables > themselves are complete, not really to ensure that writes using those > page tables are complete. > > If users of this call have additional requirements to make sure other > writes complete (which iounmap surely does) then I think they need to > have their own barriers (or further punt this up to their callers). Right, after looking to the code, write_pte has a dsb. -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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