[Xen-devel] [PATCH v1 2/4] serial: Seperate the PCI device ids and quirks.

[Konrad Rzeszutek Wilk <konrad@xxxxxxxxxx>]

This will allow us to re-use the quirks for multiple PCI
devices.

No functional change.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
---
 xen/drivers/char/ns16550.c |   66 ++++++++++++++++++++++++++++---------------
 1 files changed, 43 insertions(+), 23 deletions(-)

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index 5dd2457..06580c8 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -81,10 +81,14 @@ static struct ns16550 {
 #endif
 } ns16550_com[2] = { { 0 } };
 
-/* Defining uart config options for MMIO devices */
 struct ns16550_config_mmio {
     u16 vendor_id;
     u16 dev_id;
+    unsigned int quirk;
+};
+
+/* Defining uart config options for MMIO devices */
+struct ns16550_config_quirk {
     unsigned int reg_shift;
     unsigned int reg_width;
     unsigned int fifo_size;
@@ -95,30 +99,28 @@ struct ns16550_config_mmio {
     unsigned int first_offset;
 };
 
-
 #ifdef HAS_PCI
+enum ns16550_config_quirk_nr {
+    quirk_default = 0,
+    quirk_trumanage,
+    quirk_oxford,
+};
 /*
  * Create lookup tables for specific MMIO devices..
  * It is assumed that if the device found is MMIO,
  * then you have indexed it here. Else, the driver
  * does nothing.
  */
-static struct ns16550_config_mmio __initdata uart_config[] =
-{
-    /* Broadcom TruManage device */
-    {
-        .vendor_id = 0x14e4,
-        .dev_id = 0x160a,
+static struct ns16550_config_quirk __initdata uart_quirk[] = {
+    [quirk_default] = { }, /* Ignored. */
+    [quirk_trumanage] = {
         .reg_shift = 2,
         .reg_width = 1,
         .fifo_size = 16,
         .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
         .max_bars = 1,
     },
-    /* OXPCIe952 1 Native UART  */
-    {
-        .vendor_id = 0x1415,
-        .dev_id = 0xc138,
+    [quirk_oxford] = {
         .base_baud = 4000000,
         .uart_offset = 0x200,
         .first_offset = 0x1000,
@@ -129,6 +131,21 @@ static struct ns16550_config_mmio __initdata uart_config[] 
=
         .max_bars = 1, /* It can do more, but we would need more custom code.*/
     }
 };
+static struct ns16550_config_mmio __initdata uart_config[] =
+{
+    /* Broadcom TruManage device */
+    {
+        .vendor_id = 0x14e4,
+        .dev_id = 0x160a,
+        .quirk = quirk_trumanage,
+    },
+    /* OXPCIe952 1 Native UART  */
+    {
+        .vendor_id = 0x1415,
+        .dev_id = 0xc138,
+        .quirk = quirk_oxford,
+    }
+};
 #endif
 
 static void ns16550_delayed_resume(void *data);
@@ -695,34 +712,37 @@ pci_uart_config (struct ns16550 *uart, int skip_amt, int 
bar_idx)
                     /* Check for quirks in uart_config lookup table */
                     for ( i = 0; i < ARRAY_SIZE(uart_config); i++)
                     {
+                        unsigned int q;
+
                         if ( uart_config[i].vendor_id != vendor )
                             continue;
 
                         if ( uart_config[i].dev_id != device )
                             continue;
 
+                        q = uart_config[i].quirk;
                         /*
                          * Force length of mmio region to be at least
                          * 8 bytes times (1 << reg_shift)
                          */
-                        if ( size < (0x8 * (1 << uart_config[i].reg_shift)) )
+                        if ( size < (0x8 * (1 << uart_quirk[q].reg_shift)) )
                             continue;
 
-                        if ( bar_idx >= uart_config[i].max_bars )
+                        if ( bar_idx >= uart_quirk[q].max_bars )
                             continue;
 
-                        if ( uart_config[i].fifo_size )
-                            uart->fifo_size = uart_config[i].fifo_size;
+                        if ( uart_quirk[q].fifo_size )
+                            uart->fifo_size = uart_quirk[q].fifo_size;
 
-                        uart->reg_shift = uart_config[i].reg_shift;
-                        uart->reg_width = uart_config[i].reg_width;
-                        uart->lsr_mask = uart_config[i].lsr_mask;
+                        uart->reg_shift = uart_quirk[q].reg_shift;
+                        uart->reg_width = uart_quirk[q].reg_width;
+                        uart->lsr_mask = uart_quirk[q].lsr_mask;
                         uart->io_base = ((u64)bar_64 << 32) |
                                         (bar & PCI_BASE_ADDRESS_MEM_MASK);
-                        uart->offset = uart_config[i].first_offset;
-                        uart->offset += bar_idx * uart_config[i].uart_offset;
-                        if ( uart_config[i].base_baud )
-                            uart->clock_hz = uart_config[i].base_baud * 16;
+                        uart->offset = uart_quirk[q].first_offset;
+                        uart->offset += bar_idx * uart_quirk[q].uart_offset;
+                        if ( uart_quirk[q].base_baud )
+                            uart->clock_hz = uart_quirk[q].base_baud * 16;
                         /* Set device and MMIO region read only to Dom0 */
                         uart->enable_ro = 1;
                         break;
-- 
1.7.7.6


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