[Xen-devel] [PATCH 3/3 V3] mcheck, mce_amd: Verify presence of extended AMD_MC4_MISC registers

[Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>]

MSR 0x413 is present in all families from F10 onwards. But
the extended block of MC4 MISC registers do not exist always.
In this patch, we rework the vmce_amd_[wr|rd]msr functions
to return #GP to guest if register does not exist in HW.

If they do, then we continue current policy of blocking access
as this bank is not emulated. So for reads - return value = 0
and for writes, do nothing.

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>
Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
---
 xen/arch/x86/cpu/mcheck/amd_f10.c |   64 +++++++++++++++++--------------------
 xen/arch/x86/cpu/mcheck/mce_amd.h |    3 ++
 2 files changed, 32 insertions(+), 35 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/amd_f10.c 
b/xen/arch/x86/cpu/mcheck/amd_f10.c
index 61319dc..b1ccda4 100644
--- a/xen/arch/x86/cpu/mcheck/amd_f10.c
+++ b/xen/arch/x86/cpu/mcheck/amd_f10.c
@@ -102,46 +102,40 @@ enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 
*c)
        return mcheck_amd_famXX;
 }
 
+/* check for AMD MC4 extended MISC register presence */
+static inline int amd_thresholding_reg_present(uint32_t msr)
+{
+    uint64_t val;
+    rdmsr_safe(msr, val);
+    if ( val & (AMD_MC4_MISC_VAL_MASK | AMD_MC4_MISC_CNTP_MASK) )
+        return 1;
+
+    return 0;
+}
+
 /* amd specific MCA MSR */
 int vmce_amd_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
 {
-       switch (msr) {
-       case MSR_F10_MC4_MISC1: /* DRAM error type */
-               v->arch.vmce.bank[1].mci_misc = val; 
-               mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
-               break;
-       case MSR_F10_MC4_MISC2: /* Link error type */
-       case MSR_F10_MC4_MISC3: /* L3 cache error type */
-               /* ignore write: we do not emulate link and l3 cache errors
-                * to the guest.
-                */
-               mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
-               break;
-       default:
-               return 0;
-       }
-
-       return 1;
+    if ( msr != MSR_F10_MC4_MISC1 )
+    {
+        /* If not present, #GP fault, else do nothing as we don't emulate */
+        if ( !amd_thresholding_reg_present(msr) )
+            return -1;
+    }
+
+    mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+    return 1;
 }
 
 int vmce_amd_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
 {
-       switch (msr) {
-       case MSR_F10_MC4_MISC1: /* DRAM error type */
-               *val = v->arch.vmce.bank[1].mci_misc;
-               mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
-               break;
-       case MSR_F10_MC4_MISC2: /* Link error type */
-       case MSR_F10_MC4_MISC3: /* L3 cache error type */
-               /* we do not emulate link and l3 cache
-                * errors to the guest.
-                */
-               *val = 0;
-               mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
-               break;
-       default:
-               return 0;
-       }
-
-       return 1;
+    if ( msr != MSR_F10_MC4_MISC1 )
+    {
+        /* If not present, #GP fault, else assign '0' as we don't emulate */
+        if ( !amd_thresholding_reg_present(msr) )
+            return -1;
+    }
+
+    *val = 0;
+    return 1;
 }
diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.h 
b/xen/arch/x86/cpu/mcheck/mce_amd.h
index 5d047e7..a6024fb 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.h
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.h
@@ -1,6 +1,9 @@
 #ifndef _MCHECK_AMD_H
 #define _MCHECK_AMD_H
 
+#define AMD_MC4_MISC_VAL_MASK           (1ULL << 63)
+#define AMD_MC4_MISC_CNTP_MASK          (1ULL << 62)
+
 enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c);
 enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c);
 
-- 
1.7.9.5



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