Re: [Xen-devel] [PATCH] xen: arm: force guest memory accesses to cacheable when MMU is disabled

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Tue, 2014-01-07 at 20:39 +0000, Stefano Stabellini wrote:
> > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> > index 124cccf..104d228 100644
> > --- a/xen/arch/arm/domain.c
> > +++ b/xen/arch/arm/domain.c
> > @@ -219,6 +219,11 @@ static void ctxt_switch_to(struct vcpu *n)
> >      else
> >          hcr |= HCR_RW;
> >  
> > +    if ( n->arch.sctlr & SCTLR_M )
> > +        hcr &= ~(HCR_TVM|HCR_DC);
> > +    else
> > +        hcr |= (HCR_TVM|HCR_DC);
> > +
> >      WRITE_SYSREG(hcr, HCR_EL2);
> >      isb();
> 
> Is this actually needed? Shouldn't HCR be already correctly updated by
> update_sctlr?

Not if we are switching back and forth between two guests which are in
different states.

> > +/*
> > + * Passthru a 32-bit AArch32 register which is 64-bit under AArch64.
> > + * Updates the lower 32-bits and clears the upper bits.
> > + */
> > +#define CP32_PASSTHRU64(R...) do {              \
> > +    if ( cp32.read )                            \
> > +        *r = (uint32_t)READ_SYSREG64(R);        \
> > +    else                                        \
> > +        WRITE_SYSREG64((uint64_t)*r, R);        \
> > +} while(0)
> 
> Can/Should CP32_PASSTHRU64_LO be used instead of this?

LO preserves the upper 32-bits which this macro deliberately does not.

Now, an AArch32 guest on an AArch64 hypervisor should never have
anything else in the top bits of a register which it sees as 32-bit, so
using LO would work, but I think having it be explicit like this is
better.

Ian.


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