[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 2/2] x86/viridian: TSC and APIC Frequency MSRs
These viridian MSRs are read-only sources of the TSC and APIC frequency (in units of Hz) From: Paul Durrant <paul.durrant@xxxxxxxxxx> Signed-off-by: Paul Durrant <paul.durrant@xxxxxxxxxx> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> CC: Keir Fraser <keir@xxxxxxx> CC: Jan Beulich <JBeulich@xxxxxxxx> --- xen/arch/x86/hvm/viridian.c | 16 +++++++++++++++- xen/arch/x86/hvm/vlapic.c | 3 --- xen/include/asm-x86/hvm/vlapic.h | 3 +++ xen/include/asm-x86/perfc_defn.h | 2 ++ 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/hvm/viridian.c b/xen/arch/x86/hvm/viridian.c index f363037..2b86d66 100644 --- a/xen/arch/x86/hvm/viridian.c +++ b/xen/arch/x86/hvm/viridian.c @@ -21,6 +21,8 @@ #define VIRIDIAN_MSR_HYPERCALL 0x40000001 #define VIRIDIAN_MSR_VP_INDEX 0x40000002 #define VIRIDIAN_MSR_TIME_REF_COUNT 0x40000020 +#define VIRIDIAN_MSR_TSC_FREQUENCY 0x40000022 +#define VIRIDIAN_MSR_APIC_FREQUENCY 0x40000023 #define VIRIDIAN_MSR_EOI 0x40000070 #define VIRIDIAN_MSR_ICR 0x40000071 #define VIRIDIAN_MSR_TPR 0x40000072 @@ -38,6 +40,7 @@ #define CPUID3A_MSR_APIC_ACCESS (1 << 4) #define CPUID3A_MSR_HYPERCALL (1 << 5) #define CPUID3A_MSR_VP_INDEX (1 << 6) +#define CPUID3A_MSR_FREQ (1 << 11) /* Viridian CPUID 4000004, Implementation Recommendations. */ #define CPUID4A_MSR_BASED_APIC (1 << 3) @@ -88,7 +91,8 @@ int cpuid_viridian_leaves(unsigned int leaf, unsigned int *eax, *eax = (CPUID3A_MSR_REF_COUNT | CPUID3A_MSR_APIC_ACCESS | CPUID3A_MSR_HYPERCALL | - CPUID3A_MSR_VP_INDEX); + CPUID3A_MSR_VP_INDEX | + CPUID3A_MSR_FREQ); break; case 4: /* Recommended hypercall usage. */ @@ -313,6 +317,16 @@ int rdmsr_viridian_regs(uint32_t idx, uint64_t *val) *val = hvm_get_guest_time(v) / 100; break; + case VIRIDIAN_MSR_TSC_FREQUENCY: + perfc_incr(mshv_rdmsr_tsc_frequency); + *val = (uint64_t)d->arch.tsc_khz * 1000ull; + break; + + case VIRIDIAN_MSR_APIC_FREQUENCY: + perfc_incr(mshv_rdmsr_apic_frequency); + *val = 1000000000ull / APIC_BUS_CYCLE_NS; + break; + case VIRIDIAN_MSR_ICR: perfc_incr(mshv_rdmsr_icr); *val = (((uint64_t)vlapic_get_reg(vcpu_vlapic(v), APIC_ICR2) << 32) | diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 5c33d3a..bc06010 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -44,9 +44,6 @@ #define VLAPIC_VERSION 0x00050014 #define VLAPIC_LVT_NUM 6 -/* vlapic's frequence is 100 MHz */ -#define APIC_BUS_CYCLE_NS 10 - #define LVT_MASK \ APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK diff --git a/xen/include/asm-x86/hvm/vlapic.h b/xen/include/asm-x86/hvm/vlapic.h index eb6dec9..66f0aff 100644 --- a/xen/include/asm-x86/hvm/vlapic.h +++ b/xen/include/asm-x86/hvm/vlapic.h @@ -80,6 +80,9 @@ struct vlapic { } init_sipi; }; +/* vlapic's frequence is 100 MHz */ +#define APIC_BUS_CYCLE_NS 10 + static inline uint32_t vlapic_get_reg(struct vlapic *vlapic, uint32_t reg) { return *((uint32_t *)(&vlapic->regs->data[reg])); diff --git a/xen/include/asm-x86/perfc_defn.h b/xen/include/asm-x86/perfc_defn.h index bd251f5..6c590aa 100644 --- a/xen/include/asm-x86/perfc_defn.h +++ b/xen/include/asm-x86/perfc_defn.h @@ -119,6 +119,8 @@ PERFCOUNTER(mshv_rdmsr_osid, "MS Hv rdmsr Guest OS ID") PERFCOUNTER(mshv_rdmsr_hc_page, "MS Hv rdmsr hypercall page") PERFCOUNTER(mshv_rdmsr_vp_index, "MS Hv rdmsr vp index") PERFCOUNTER(mshv_rdmsr_time_ref_count, "MS Hv rdmsr time reference count") +PERFCOUNTER(mshv_rdmsr_tsc_frequency, "MS Hv rdmsr TSC frequency") +PERFCOUNTER(mshv_rdmsr_apic_frequency, "MS Hv rdmsr APIC frequency") PERFCOUNTER(mshv_rdmsr_icr, "MS Hv rdmsr icr") PERFCOUNTER(mshv_rdmsr_tpr, "MS Hv rdmsr tpr") PERFCOUNTER(mshv_rdmsr_apic_assist, "MS Hv rdmsr APIC assist") -- 1.7.10.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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