[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 2/6] xen: arm: Enable 40 bit addressing in VTCR for arm64
This requires setting the v8 specific VTCR_EL2.PS field. These bits are UNK/SBZP on v7. Also the TS0SZ field is described slightly differently for v8, so update the comment to reflect this. Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx> --- xen/arch/arm/mm.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 474dfef..16bbb39 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -369,9 +369,16 @@ void __cpuinit setup_virt_paging(void) /* Setup Stage 2 address translation */ /* SH0=00, ORGN0=IRGN0=01 * SL0=01 (Level-1) - * T0SZ=(1)1000 = -8 (40 bit physical addresses) + * ARVv7: T0SZ=(1)1000 = -8 (32-(-8) = 40 bit physical addresses) + * ARMv8: T0SZ=01 1000 = 24 (64-24 = 40 bit physical addresses) + * PS=010 == 40 bits */ - WRITE_SYSREG32(0x80002558, VTCR_EL2); isb(); +#ifdef CONFIG_ARM_32 + WRITE_SYSREG32(0x80002558, VTCR_EL2); +#else + WRITE_SYSREG32(0x80022558, VTCR_EL2); +#endif + isb(); } static inline lpae_t pte_of_xenaddr(vaddr_t va) -- 1.7.10.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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