[Xen-devel] [PATCH v3 10/11] xen: arm: configure TCR_EL2 for 40 bit physical address space

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
Acked-by: Tim Deegan <tim@xxxxxxx>
---
 xen/arch/arm/arm64/head.S |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 3dd71af..40a0ebe 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -224,12 +224,12 @@ skip_bss:
         msr   mair_el2, x0
 
         /* Set up the HTCR:
-         * PASize -- 4G
+         * PASize -- 40 bits / 1TB
          * Top byte is used
          * PT walks use Outer-Shareable accesses,
          * PT walks are write-back, write-allocate in both cache levels,
          * Full 64-bit address space goes through this table. */
-        ldr   x0, =0x80802500
+        ldr   x0, =0x80822500
         msr   tcr_el2, x0
 
         /* Set up the SCTLR_EL2:
-- 
1.7.10.4


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