Re: [Xen-devel] [PATCH v2 10/13] x86/PMU: Add support for PMU registes handling on PV guests

[Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>]

On 09/25/2013 10:23 AM, Jan Beulich wrote:
> > > > On 20.09.13 at 11:42, Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> wrote:
> > Intercept accesses to PMU MSRs and LVTPC APIC vector (only
> > APIC_LVT_MASKED bit is processed) and process them in VPMU
> > module.
> Having scrolled through this more than once, I still can't see where
> any APIC interception is happening here.
It's not. This commit message is a a leftover from pre-v1 
implementation. LVTPC
is now updated via an explicit hypercall.

> > @@ -2574,6 +2587,24 @@ static int emulate_privileged_op(struct cpu_user_regs 
> > *regs)
> >               regs->eax = (uint32_t)msr_content;
> >               regs->edx = (uint32_t)(msr_content >> 32);
> >               break;
> > +        case MSR_IA32_PERF_CAPABILITIES:
> > +            if ( rdmsr_safe(regs->ecx, msr_content) )
> > +                goto fail;
> > +            /* Full-Width Writes not supported */
> > +            regs->eax = (uint32_t)msr_content & ~(1 << 13);
> > +            regs->edx = (uint32_t)(msr_content >> 32);
> Rather than black listing, please white list know good features
> here.
This 'case' is gone after I rebased to latest sources (we implement 
full-width writes now).
-boris

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