[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 06/13] x86/PMU: Add public xenpmu.h
Add xenpmu.h header file, move various macros and structures that will be shared between hypervisor and PV guests to it. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> --- xen/arch/x86/hvm/svm/vpmu.c | 15 +++----- xen/arch/x86/hvm/vmx/vpmu_core2.c | 43 ++++++++++++---------- xen/arch/x86/hvm/vpmu.c | 1 + xen/arch/x86/oprofile/op_model_ppro.c | 6 +++- xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 32 ----------------- xen/include/asm-x86/hvm/vpmu.h | 10 ++---- xen/include/public/arch-x86/xenpmu-x86.h | 62 ++++++++++++++++++++++++++++++++ xen/include/public/xenpmu.h | 38 ++++++++++++++++++++ 8 files changed, 136 insertions(+), 71 deletions(-) delete mode 100644 xen/include/asm-x86/hvm/vmx/vpmu_core2.h create mode 100644 xen/include/public/arch-x86/xenpmu-x86.h create mode 100644 xen/include/public/xenpmu.h diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c index a09930e..25532d0 100644 --- a/xen/arch/x86/hvm/svm/vpmu.c +++ b/xen/arch/x86/hvm/svm/vpmu.c @@ -30,10 +30,7 @@ #include <asm/apic.h> #include <asm/hvm/vlapic.h> #include <asm/hvm/vpmu.h> - -#define F10H_NUM_COUNTERS 4 -#define F15H_NUM_COUNTERS 6 -#define MAX_NUM_COUNTERS F15H_NUM_COUNTERS +#include <public/xenpmu.h> #define MSR_F10H_EVNTSEL_GO_SHIFT 40 #define MSR_F10H_EVNTSEL_EN_SHIFT 22 @@ -49,6 +46,9 @@ static const u32 __read_mostly *counters; static const u32 __read_mostly *ctrls; static bool_t __read_mostly k7_counters_mirrored; +#define F10H_NUM_COUNTERS 4 +#define F15H_NUM_COUNTERS 6 + /* PMU Counter MSRs. */ static const u32 AMD_F10H_COUNTERS[] = { MSR_K7_PERFCTR0, @@ -83,13 +83,6 @@ static const u32 AMD_F15H_CTRLS[] = { MSR_AMD_FAM15H_EVNTSEL5 }; -/* storage for context switching */ -struct amd_vpmu_context { - u64 counters[MAX_NUM_COUNTERS]; - u64 ctrls[MAX_NUM_COUNTERS]; - bool_t msr_bitmap_set; -}; - static inline int get_pmu_reg_type(u32 addr) { if ( (addr >= MSR_K7_EVNTSEL0) && (addr <= MSR_K7_EVNTSEL3) ) diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c index 50f784f..7d1da3f 100644 --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c @@ -35,8 +35,8 @@ #include <asm/hvm/vmx/vmcs.h> #include <public/sched.h> #include <public/hvm/save.h> +#include <public/xenpmu.h> #include <asm/hvm/vpmu.h> -#include <asm/hvm/vmx/vpmu_core2.h> /* * See Intel SDM Vol 2a Instruction Set Reference chapter 3 for CPUID @@ -64,6 +64,10 @@ #define PMU_FIXED_WIDTH_BITS 8 /* 8 bits 5..12 */ #define PMU_FIXED_WIDTH_MASK (((1 << PMU_FIXED_WIDTH_BITS) -1) << PMU_FIXED_WIDTH_SHIFT) +/* Intel-specific VPMU features */ +#define VPMU_CPU_HAS_DS 0x100 /* Has Debug Store */ +#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */ + /* * MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed * counters. 4 bits for every counter. @@ -71,16 +75,6 @@ #define FIXED_CTR_CTRL_BITS 4 #define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1) -#define VPMU_CORE2_MAX_FIXED_PMCS 4 -struct core2_vpmu_context { - u64 fixed_ctrl; - u64 ds_area; - u64 pebs_enable; - u64 global_ovf_status; - u64 fix_counters[VPMU_CORE2_MAX_FIXED_PMCS]; - struct arch_msr_pair arch_msr_pair[1]; -}; - static int arch_pmc_cnt; /* Number of general-purpose performance counters */ static int fixed_pmc_cnt; /* Number of fixed performance counters */ @@ -225,6 +219,7 @@ static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index) return 0; } +#define msraddr_to_bitpos(x) (((x)&0xffff) + ((x)>>31)*0x2000) static void core2_vpmu_set_msr_bitmap(unsigned long *msr_bitmap) { int i; @@ -349,8 +344,7 @@ static int core2_vpmu_alloc_resource(struct vcpu *v) vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, core2_calc_intial_glb_ctrl_msr()); - core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) + - (arch_pmc_cnt-1)*sizeof(struct arch_msr_pair)); + core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context)); if ( !core2_vpmu_cxt ) goto out_err; @@ -614,6 +608,18 @@ static void core2_vpmu_do_cpuid(unsigned int input, *ecx |= cpufeat_mask(X86_FEATURE_DSCPL); } } + else if ( input == 0xa ) + { + /* Limit number of counters to max that we support */ + if ( ((*eax & PMU_GENERAL_NR_MASK) >> PMU_GENERAL_NR_SHIFT) > + XENPMU_CORE2_MAX_ARCH_PMCS ) + *eax = (*eax & ~PMU_GENERAL_NR_MASK) | + (XENPMU_CORE2_MAX_ARCH_PMCS << PMU_GENERAL_NR_SHIFT); + if ( ((*edx & PMU_FIXED_NR_MASK) >> PMU_FIXED_NR_SHIFT) > + XENPMU_CORE2_MAX_FIXED_PMCS ) + *eax = (*eax & ~PMU_FIXED_NR_MASK) | + (XENPMU_CORE2_MAX_FIXED_PMCS << PMU_FIXED_NR_SHIFT); + } } /* Dump vpmu info on console, called in the context of keyhandler 'q'. */ @@ -641,11 +647,10 @@ static void core2_vpmu_dump(struct vcpu *v) /* Print the contents of the counter and its configuration msr. */ for ( i = 0; i < arch_pmc_cnt; i++ ) - { - struct arch_msr_pair* msr_pair = core2_vpmu_cxt->arch_msr_pair; printk(" general_%d: 0x%016lx ctrl: 0x%016lx\n", - i, msr_pair[i].counter, msr_pair[i].control); - } + i, core2_vpmu_cxt->arch_msr_pair[i].counter, + core2_vpmu_cxt->arch_msr_pair[i].control); + /* * The configuration of the fixed counter is 4 bits each in the * MSR_CORE_PERF_FIXED_CTR_CTRL. @@ -739,8 +744,8 @@ func_out: arch_pmc_cnt = core2_get_arch_pmc_count(); fixed_pmc_cnt = core2_get_fixed_pmc_count(); - if ( fixed_pmc_cnt > VPMU_CORE2_MAX_FIXED_PMCS ) - fixed_pmc_cnt = VPMU_CORE2_MAX_FIXED_PMCS; + if ( fixed_pmc_cnt > XENPMU_CORE2_MAX_FIXED_PMCS ) + fixed_pmc_cnt = XENPMU_CORE2_MAX_FIXED_PMCS; check_pmc_quirk(); return 0; diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c index d6a9ff6..fa8cfd7 100644 --- a/xen/arch/x86/hvm/vpmu.c +++ b/xen/arch/x86/hvm/vpmu.c @@ -31,6 +31,7 @@ #include <asm/hvm/svm/svm.h> #include <asm/hvm/svm/vmcb.h> #include <asm/apic.h> +#include <public/xenpmu.h> /* * "vpmu" : vpmu generally enabled diff --git a/xen/arch/x86/oprofile/op_model_ppro.c b/xen/arch/x86/oprofile/op_model_ppro.c index 3225937..5aae2e7 100644 --- a/xen/arch/x86/oprofile/op_model_ppro.c +++ b/xen/arch/x86/oprofile/op_model_ppro.c @@ -20,11 +20,15 @@ #include <asm/regs.h> #include <asm/current.h> #include <asm/hvm/vpmu.h> -#include <asm/hvm/vmx/vpmu_core2.h> #include "op_x86_model.h" #include "op_counter.h" +struct arch_msr_pair { + u64 counter; + u64 control; +}; + /* * Intel "Architectural Performance Monitoring" CPUID * detection/enumeration details: diff --git a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h b/xen/include/asm-x86/hvm/vmx/vpmu_core2.h deleted file mode 100644 index 410372d..0000000 --- a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h +++ /dev/null @@ -1,32 +0,0 @@ - -/* - * vpmu_core2.h: CORE 2 specific PMU virtualization for HVM domain. - * - * Copyright (c) 2007, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - * Author: Haitao Shan <haitao.shan@xxxxxxxxx> - */ - -#ifndef __ASM_X86_HVM_VPMU_CORE_H_ -#define __ASM_X86_HVM_VPMU_CORE_H_ - -struct arch_msr_pair { - u64 counter; - u64 control; -}; - -#endif /* __ASM_X86_HVM_VPMU_CORE_H_ */ - diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h index 674cdad..50cdc4f 100644 --- a/xen/include/asm-x86/hvm/vpmu.h +++ b/xen/include/asm-x86/hvm/vpmu.h @@ -22,6 +22,8 @@ #ifndef __ASM_X86_HVM_VPMU_H_ #define __ASM_X86_HVM_VPMU_H_ +#include <public/xenpmu.h> + /* * Flag bits given as a string on the hypervisor boot parameter 'vpmu'. * See arch/x86/hvm/vpmu.c. @@ -29,12 +31,9 @@ #define VPMU_BOOT_ENABLED 0x1 /* vpmu generally enabled. */ #define VPMU_BOOT_BTS 0x2 /* Intel BTS feature wanted. */ - -#define msraddr_to_bitpos(x) (((x)&0xffff) + ((x)>>31)*0x2000) #define vcpu_vpmu(vcpu) (&((vcpu)->arch.hvm_vcpu.vpmu)) #define vpmu_vcpu(vpmu) (container_of((vpmu), struct vcpu, \ arch.hvm_vcpu.vpmu)) -#define vpmu_domain(vpmu) (vpmu_vcpu(vpmu)->domain) #define MSR_TYPE_COUNTER 0 #define MSR_TYPE_CTRL 1 @@ -76,11 +75,6 @@ struct vpmu_struct { #define VPMU_FROZEN 0x10 /* Stop counters while VCPU is not running */ #define VPMU_PASSIVE_DOMAIN_ALLOCATED 0x20 -/* VPMU features */ -#define VPMU_CPU_HAS_DS 0x100 /* Has Debug Store */ -#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */ - - #define vpmu_set(_vpmu, _x) ((_vpmu)->flags |= (_x)) #define vpmu_reset(_vpmu, _x) ((_vpmu)->flags &= ~(_x)) #define vpmu_is_set(_vpmu, _x) ((_vpmu)->flags & (_x)) diff --git a/xen/include/public/arch-x86/xenpmu-x86.h b/xen/include/public/arch-x86/xenpmu-x86.h new file mode 100644 index 0000000..04e02b3 --- /dev/null +++ b/xen/include/public/arch-x86/xenpmu-x86.h @@ -0,0 +1,62 @@ +#ifndef __XEN_PUBLIC_ARCH_X86_PMU_H__ +#define __XEN_PUBLIC_ARCH_X86_PMU_H__ + +/* x86-specific PMU definitions */ + + +/* AMD PMU registers and structures */ +#define XENPMU_AMD_MAX_COUNTERS 16 /* To accommodate more counters in */ + /* the future (e.g. NB counters) */ +struct amd_vpmu_context { + uint64_t counters[XENPMU_AMD_MAX_COUNTERS]; + uint64_t ctrls[XENPMU_AMD_MAX_COUNTERS]; + uint8_t msr_bitmap_set; /* Used by HVM only */ +}; + +/* Intel PMU registers and structures */ +#define XENPMU_CORE2_MAX_ARCH_PMCS 16 +#define XENPMU_CORE2_MAX_FIXED_PMCS 4 +struct core2_vpmu_context { + uint64_t global_ctrl; + uint64_t global_ovf_ctrl; + uint64_t global_status; + uint64_t global_ovf_status; + uint64_t fixed_ctrl; + uint64_t ds_area; + uint64_t pebs_enable; + uint64_t debugctl; + uint64_t fix_counters[XENPMU_CORE2_MAX_FIXED_PMCS]; + struct { + uint64_t counter; + uint64_t control; + } arch_msr_pair[XENPMU_CORE2_MAX_ARCH_PMCS]; +}; + +#define MAX(x, y) ((x) > (y) ? (x) : (y)) +#define XENPMU_MAX_CTXT_SZ MAX(sizeof(struct amd_vpmu_context),\ + sizeof(struct core2_vpmu_context)) +#define XENPMU_CTXT_PAD_SZ (((XENPMU_MAX_CTXT_SZ + 64) & ~63) + 128) +struct arch_xenpmu { + union { + struct cpu_user_regs regs; + uint8_t pad2[256]; + }; + union { + struct amd_vpmu_context amd; + struct core2_vpmu_context intel; + uint8_t pad1[XENPMU_CTXT_PAD_SZ]; + }; +}; +typedef struct arch_xenpmu arch_xenpmu_t; + +#endif /* __XEN_PUBLIC_ARCH_X86_PMU_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/public/xenpmu.h b/xen/include/public/xenpmu.h new file mode 100644 index 0000000..fbacd7e --- /dev/null +++ b/xen/include/public/xenpmu.h @@ -0,0 +1,38 @@ +#ifndef __XEN_PUBLIC_XENPMU_H__ +#define __XEN_PUBLIC_XENPMU_H__ + +#include "xen.h" +#if defined(__i386__) || defined(__x86_64__) +#include "arch-x86/xenpmu-x86.h" +#elif defined (__arm__) || defined (__aarch64__) +#include "arch-arm.h" +#else +#error "Unsupported architecture" +#endif + +#define XENPMU_VER_MAJ 0 +#define XENPMU_VER_MIN 0 + + +/* Shared between hypervisor and PV domain */ +struct xenpmu_data { + uint32_t domain_id; + uint32_t vcpu_id; + uint32_t pcpu_id; + uint32_t pmu_flags; + + arch_xenpmu_t pmu; +}; +typedef struct xenpmu_data xenpmu_data_t; + +#endif /* __XEN_PUBLIC_XENPMU_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ -- 1.8.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
|
Lists.xenproject.org is hosted with RackSpace, monitoring our |