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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v1 06/13] x86/PMU: Add public xenpmu.h
Add xenpmu.h header file, move various macros and structures that will be
shared between hypervisor and PV guests to it.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
---
xen/arch/x86/hvm/svm/vpmu.c | 12 +---
xen/arch/x86/hvm/vmx/vpmu_core2.c | 43 +++----------
xen/arch/x86/hvm/vpmu.c | 5 +-
xen/arch/x86/oprofile/op_model_ppro.c | 1 -
xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 32 ----------
xen/include/asm-x86/hvm/vpmu.h | 14 +----
xen/include/public/xenpmu.h | 101 +++++++++++++++++++++++++++++++
7 files changed, 115 insertions(+), 93 deletions(-)
delete mode 100644 xen/include/asm-x86/hvm/vmx/vpmu_core2.h
create mode 100644 xen/include/public/xenpmu.h
diff --git a/xen/arch/x86/hvm/svm/vpmu.c b/xen/arch/x86/hvm/svm/vpmu.c
index a09930e..9f9c9ea 100644
--- a/xen/arch/x86/hvm/svm/vpmu.c
+++ b/xen/arch/x86/hvm/svm/vpmu.c
@@ -30,10 +30,7 @@
#include <asm/apic.h>
#include <asm/hvm/vlapic.h>
#include <asm/hvm/vpmu.h>
-
-#define F10H_NUM_COUNTERS 4
-#define F15H_NUM_COUNTERS 6
-#define MAX_NUM_COUNTERS F15H_NUM_COUNTERS
+#include <public/xenpmu.h>
#define MSR_F10H_EVNTSEL_GO_SHIFT 40
#define MSR_F10H_EVNTSEL_EN_SHIFT 22
@@ -83,13 +80,6 @@ static const u32 AMD_F15H_CTRLS[] = {
MSR_AMD_FAM15H_EVNTSEL5
};
-/* storage for context switching */
-struct amd_vpmu_context {
- u64 counters[MAX_NUM_COUNTERS];
- u64 ctrls[MAX_NUM_COUNTERS];
- bool_t msr_bitmap_set;
-};
-
static inline int get_pmu_reg_type(u32 addr)
{
if ( (addr >= MSR_K7_EVNTSEL0) && (addr <= MSR_K7_EVNTSEL3) )
diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c
b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 30a948e..f3b6de0 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -35,8 +35,8 @@
#include <asm/hvm/vmx/vmcs.h>
#include <public/sched.h>
#include <public/hvm/save.h>
+#include <public/xenpmu.h>
#include <asm/hvm/vpmu.h>
-#include <asm/hvm/vmx/vpmu_core2.h>
/*
* See Intel SDM Vol 2a Instruction Set Reference chapter 3 for CPUID
@@ -64,12 +64,10 @@
#define PMU_FIXED_WIDTH_BITS 8 /* 8 bits 5..12 */
#define PMU_FIXED_WIDTH_MASK (((1 << PMU_FIXED_WIDTH_BITS) -1) <<
PMU_FIXED_WIDTH_SHIFT)
-static const u32 core2_fix_counters_msr[] = {
- MSR_CORE_PERF_FIXED_CTR0,
- MSR_CORE_PERF_FIXED_CTR1,
- MSR_CORE_PERF_FIXED_CTR2
-};
-#define VPMU_CORE2_NUM_FIXED (sizeof(core2_fix_counters_msr) / sizeof(u32))
+
+/* Intel-specific VPMU features */
+#define VPMU_CPU_HAS_DS 0x100 /* Has Debug Store */
+#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */
/*
* MSR_CORE_PERF_FIXED_CTR_CTRL contains the configuration of all fixed
@@ -81,28 +79,6 @@ static const u32 core2_fix_counters_msr[] = {
/* The index into the core2_ctrls_msr[] of this MSR used in core2_vpmu_dump()
*/
#define MSR_CORE_PERF_FIXED_CTR_CTRL_IDX 0
-/* Core 2 Non-architectual Performance Control MSRs. */
-static const u32 core2_ctrls_msr[] = {
- MSR_CORE_PERF_FIXED_CTR_CTRL,
- MSR_IA32_PEBS_ENABLE,
- MSR_IA32_DS_AREA
-};
-#define VPMU_CORE2_NUM_CTRLS (sizeof(core2_ctrls_msr) / sizeof(u32))
-
-struct core2_pmu_enable {
- char ds_area_enable;
- char fixed_ctr_enable[VPMU_CORE2_NUM_FIXED];
- char arch_pmc_enable[1];
-};
-
-struct core2_vpmu_context {
- struct core2_pmu_enable *pmu_enable;
- u64 fix_counters[VPMU_CORE2_NUM_FIXED];
- u64 ctrls[VPMU_CORE2_NUM_CTRLS];
- u64 global_ovf_status;
- struct arch_msr_pair arch_msr_pair[1];
-};
-
static int arch_pmc_cnt; /* Number of general-purpose performance counters */
/*
@@ -237,6 +213,7 @@ static int is_core2_vpmu_msr(u32 msr_index, int *type, int
*index)
return 0;
}
+#define msraddr_to_bitpos(x) (((x)&0xffff) + ((x)>>31)*0x2000)
static void core2_vpmu_set_msr_bitmap(unsigned long *msr_bitmap)
{
int i;
@@ -355,13 +332,11 @@ static int core2_vpmu_alloc_resource(struct vcpu *v)
vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL,
core2_calc_intial_glb_ctrl_msr());
- pmu_enable = xzalloc_bytes(sizeof(struct core2_pmu_enable) +
- arch_pmc_cnt - 1);
+ pmu_enable = xzalloc_bytes(sizeof(struct core2_pmu_enable));
if ( !pmu_enable )
goto out_err;
- core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context) +
- (arch_pmc_cnt-1)*sizeof(struct arch_msr_pair));
+ core2_vpmu_cxt = xzalloc_bytes(sizeof(struct core2_vpmu_context));
if ( !core2_vpmu_cxt )
goto out_err;
@@ -730,7 +705,7 @@ static int core2_vpmu_initialise(struct vcpu *v, unsigned
int vpmu_flags)
u64 msr_content;
struct cpuinfo_x86 *c = ¤t_cpu_data;
- if ( !(vpmu_flags & VPMU_BOOT_BTS) )
+ if ( !(vpmu_flags & VPMU_INTEL_BTS) )
goto func_out;
/* Check the 'Debug Store' feature in the CPUID.EAX[1]:EDX[21] */
if ( cpu_has(c, X86_FEATURE_DS) )
diff --git a/xen/arch/x86/hvm/vpmu.c b/xen/arch/x86/hvm/vpmu.c
index d6a9ff6..768f766 100644
--- a/xen/arch/x86/hvm/vpmu.c
+++ b/xen/arch/x86/hvm/vpmu.c
@@ -31,6 +31,7 @@
#include <asm/hvm/svm/svm.h>
#include <asm/hvm/svm/vmcb.h>
#include <asm/apic.h>
+#include <public/xenpmu.h>
/*
* "vpmu" : vpmu generally enabled
@@ -51,7 +52,7 @@ static void __init parse_vpmu_param(char *s)
break;
default:
if ( !strcmp(s, "bts") )
- opt_vpmu_enabled |= VPMU_BOOT_BTS;
+ opt_vpmu_enabled |= VPMU_INTEL_BTS;
else if ( *s )
{
printk("VPMU: unknown flag: %s - vpmu disabled!\n", s);
@@ -59,7 +60,7 @@ static void __init parse_vpmu_param(char *s)
}
/* fall through */
case 1:
- opt_vpmu_enabled |= VPMU_BOOT_ENABLED;
+ opt_vpmu_enabled |= VPMU_ON;
break;
}
}
diff --git a/xen/arch/x86/oprofile/op_model_ppro.c
b/xen/arch/x86/oprofile/op_model_ppro.c
index 3225937..2939a40 100644
--- a/xen/arch/x86/oprofile/op_model_ppro.c
+++ b/xen/arch/x86/oprofile/op_model_ppro.c
@@ -20,7 +20,6 @@
#include <asm/regs.h>
#include <asm/current.h>
#include <asm/hvm/vpmu.h>
-#include <asm/hvm/vmx/vpmu_core2.h>
#include "op_x86_model.h"
#include "op_counter.h"
diff --git a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
b/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
deleted file mode 100644
index 410372d..0000000
--- a/xen/include/asm-x86/hvm/vmx/vpmu_core2.h
+++ /dev/null
@@ -1,32 +0,0 @@
-
-/*
- * vpmu_core2.h: CORE 2 specific PMU virtualization for HVM domain.
- *
- * Copyright (c) 2007, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Author: Haitao Shan <haitao.shan@xxxxxxxxx>
- */
-
-#ifndef __ASM_X86_HVM_VPMU_CORE_H_
-#define __ASM_X86_HVM_VPMU_CORE_H_
-
-struct arch_msr_pair {
- u64 counter;
- u64 control;
-};
-
-#endif /* __ASM_X86_HVM_VPMU_CORE_H_ */
-
diff --git a/xen/include/asm-x86/hvm/vpmu.h b/xen/include/asm-x86/hvm/vpmu.h
index 674cdad..410ad12 100644
--- a/xen/include/asm-x86/hvm/vpmu.h
+++ b/xen/include/asm-x86/hvm/vpmu.h
@@ -22,19 +22,12 @@
#ifndef __ASM_X86_HVM_VPMU_H_
#define __ASM_X86_HVM_VPMU_H_
-/*
- * Flag bits given as a string on the hypervisor boot parameter 'vpmu'.
- * See arch/x86/hvm/vpmu.c.
- */
-#define VPMU_BOOT_ENABLED 0x1 /* vpmu generally enabled. */
-#define VPMU_BOOT_BTS 0x2 /* Intel BTS feature wanted. */
+#include <public/xenpmu.h>
-#define msraddr_to_bitpos(x) (((x)&0xffff) + ((x)>>31)*0x2000)
#define vcpu_vpmu(vcpu) (&((vcpu)->arch.hvm_vcpu.vpmu))
#define vpmu_vcpu(vpmu) (container_of((vpmu), struct vcpu, \
arch.hvm_vcpu.vpmu))
-#define vpmu_domain(vpmu) (vpmu_vcpu(vpmu)->domain)
#define MSR_TYPE_COUNTER 0
#define MSR_TYPE_CTRL 1
@@ -76,11 +69,6 @@ struct vpmu_struct {
#define VPMU_FROZEN 0x10 /* Stop counters while VCPU
is not running */
#define VPMU_PASSIVE_DOMAIN_ALLOCATED 0x20
-/* VPMU features */
-#define VPMU_CPU_HAS_DS 0x100 /* Has Debug Store */
-#define VPMU_CPU_HAS_BTS 0x200 /* Has Branch Trace Store */
-
-
#define vpmu_set(_vpmu, _x) ((_vpmu)->flags |= (_x))
#define vpmu_reset(_vpmu, _x) ((_vpmu)->flags &= ~(_x))
#define vpmu_is_set(_vpmu, _x) ((_vpmu)->flags & (_x))
diff --git a/xen/include/public/xenpmu.h b/xen/include/public/xenpmu.h
new file mode 100644
index 0000000..420b674
--- /dev/null
+++ b/xen/include/public/xenpmu.h
@@ -0,0 +1,101 @@
+#ifndef __XEN_PUBLIC_XENPMU_H__
+#define __XEN_PUBLIC_XENPMU_H__
+
+#include <asm/msr.h>
+
+#include "xen.h"
+
+#define XENPMU_VER_MAJ 0
+#define XENPMU_VER_MIN 0
+
+/* VPMU modes */
+#define VPMU_MODE_MASK 0xff
+#define VPMU_OFF 0
+/* guests can profile themselves, (dom0 profiles itself and Xen) */
+#define VPMU_ON (1<<0)
+/*
+ * Only dom0 has access to VPMU and it profiles everyone: itself,
+ * the hypervisor and the guests.
+ */
+#define VPMU_PRIV (1<<1)
+
+/* VPMU flags */
+#define VPMU_FLAGS_MASK ((uint32_t)(~VPMU_MODE_MASK))
+#define VPMU_INTEL_BTS (1<<8) /* Ignored on AMD */
+
+
+/* AMD PMU registers and structures */
+#define F10H_NUM_COUNTERS 4
+#define F15H_NUM_COUNTERS 6
+/* To accommodate more counters in the future (e.g. NB counters) */
+#define MAX_NUM_COUNTERS 16
+struct amd_vpmu_context {
+ uint64_t counters[MAX_NUM_COUNTERS];
+ uint64_t ctrls[MAX_NUM_COUNTERS];
+ uint8_t msr_bitmap_set;
+};
+
+
+/* Intel PMU registers and structures */
+static const uint32_t core2_fix_counters_msr[] = {
+ MSR_CORE_PERF_FIXED_CTR0,
+ MSR_CORE_PERF_FIXED_CTR1,
+ MSR_CORE_PERF_FIXED_CTR2
+};
+#define VPMU_CORE2_NUM_FIXED (sizeof(core2_fix_counters_msr) /
sizeof(uint32_t))
+
+/* Core 2 Non-architectual Performance Control MSRs. */
+static const uint32_t core2_ctrls_msr[] = {
+ MSR_CORE_PERF_FIXED_CTR_CTRL,
+ MSR_IA32_PEBS_ENABLE,
+ MSR_IA32_DS_AREA
+};
+#define VPMU_CORE2_NUM_CTRLS (sizeof(core2_ctrls_msr) / sizeof(uint32_t))
+
+#define VPMU_CORE2_MAX_ARCH_PMCS 16
+struct core2_pmu_enable {
+ char ds_area_enable;
+ char fixed_ctr_enable[VPMU_CORE2_NUM_FIXED];
+ char arch_pmc_enable[VPMU_CORE2_MAX_ARCH_PMCS];
+};
+
+struct arch_msr_pair {
+ uint64_t counter;
+ uint64_t control;
+};
+struct core2_vpmu_context {
+ struct core2_pmu_enable *pmu_enable;
+ uint64_t fix_counters[VPMU_CORE2_NUM_FIXED];
+ uint64_t ctrls[VPMU_CORE2_NUM_CTRLS];
+ uint64_t global_ovf_status;
+ struct arch_msr_pair arch_msr_pair[VPMU_CORE2_MAX_ARCH_PMCS];
+};
+
+/* PMU flags */
+#define PMU_CACHED 1
+
+/* Shared between hypervisor and PV domain */
+typedef struct xenpmu_data {
+ struct cpu_user_regs regs;
+ uint16_t domain_id;
+ uint32_t vcpu_id;
+ uint32_t pcpu_id;
+ uint32_t pmu_flags;
+ union {
+ struct amd_vpmu_context amd;
+ struct core2_vpmu_context intel;
+ } pmu;
+} xenpmu_data_t;
+
+
+#endif /* __XEN_PUBLIC_XENPMU_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.8.1.4
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