[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 2/7] xen/arm: use cpumask_t to describe cpu mask in gic_route_dt_irq
On Fri, 2013-08-30 at 14:30 +0100, Julien Grall wrote: > The mapping between logical ID and GIC cpu ID can differs. Currently the code > uses unsigned int for the cpu mask. Replace by cpumask_t to take advante of > cpumask_* helpers. "advantage" In fact this replacement is all this patch does, there is no introduction of a logical map here, that comes in patch #4? The commit message made me thing otherwise. I think you could drop all but the last sentence. The rest belongs in patch #4. > > Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx> > --- > xen/arch/arm/gic.c | 20 ++++++++++++-------- > xen/arch/arm/time.c | 6 +++--- > xen/include/asm-arm/gic.h | 3 ++- > 3 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c > index a43ec23..37a73fb 100644 > --- a/xen/arch/arm/gic.c > +++ b/xen/arch/arm/gic.c > @@ -201,10 +201,14 @@ void gic_irq_disable(struct irq_desc *desc) > > /* needs to be called with gic.lock held */ > static void gic_set_irq_properties(unsigned int irq, bool_t level, > - unsigned int cpu_mask, unsigned int priority) > + const cpumask_t *cpu_mask, > + unsigned int priority) > { > volatile unsigned char *bytereg; > uint32_t cfg, edgebit; > + unsigned int mask = cpumask_bits(cpu_mask)[0]; > + > + ASSERT(!(mask & ~0xff)); /* Target bitmap only support 8 CPUS */ > > /* Set edge / level */ > cfg = GICD[GICD_ICFGR + irq / 16]; > @@ -217,7 +221,7 @@ static void gic_set_irq_properties(unsigned int irq, > bool_t level, > > /* Set target CPU mask (RAZ/WI on uniprocessor) */ > bytereg = (unsigned char *) (GICD + GICD_ITARGETSR); > - bytereg[irq] = cpu_mask; > + bytereg[irq] = mask; > > /* Set priority */ > bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR); > @@ -227,12 +231,11 @@ static void gic_set_irq_properties(unsigned int irq, > bool_t level, > > /* Program the GIC to route an interrupt */ > static int gic_route_irq(unsigned int irq, bool_t level, > - unsigned int cpu_mask, unsigned int priority) > + const cpumask_t *cpu_mask, unsigned int priority) > { > struct irq_desc *desc = irq_to_desc(irq); > unsigned long flags; > > - ASSERT(!(cpu_mask & ~0xff)); /* Targets bitmap only supports 8 CPUs */ > ASSERT(priority <= 0xff); /* Only 8 bits of priority */ > ASSERT(irq < gic.lines); /* Can't route interrupts that don't exist > */ > > @@ -259,7 +262,7 @@ static int gic_route_irq(unsigned int irq, bool_t level, > } > > /* Program the GIC to route an interrupt with a dt_irq */ > -void gic_route_dt_irq(const struct dt_irq *irq, unsigned int cpu_mask, > +void gic_route_dt_irq(const struct dt_irq *irq, const cpumask_t *cpu_mask, > unsigned int priority) > { > bool_t level; > @@ -508,7 +511,7 @@ void gic_disable_cpu(void) > void gic_route_ppis(void) > { > /* GIC maintenance */ > - gic_route_dt_irq(&gic.maintenance, 1u << smp_processor_id(), 0xa0); > + gic_route_dt_irq(&gic.maintenance, cpumask_of(smp_processor_id()), 0xa0); > /* Route timer interrupt */ > route_timer_interrupt(); > } > @@ -523,7 +526,7 @@ void gic_route_spis(void) > if ( (irq = serial_dt_irq(seridx)) == NULL ) > continue; > > - gic_route_dt_irq(irq, 1u << smp_processor_id(), 0xa0); > + gic_route_dt_irq(irq, cpumask_of(smp_processor_id()), 0xa0); > } > } > > @@ -765,7 +768,8 @@ int gic_route_irq_to_guest(struct domain *d, const struct > dt_irq *irq, > > level = dt_irq_is_level_triggered(irq); > > - gic_set_irq_properties(irq->irq, level, 1u << smp_processor_id(), 0xa0); > + gic_set_irq_properties(irq->irq, level, cpumask_of(smp_processor_id()), > + 0xa0); > > retval = __setup_irq(desc, irq->irq, action); > if (retval) { > diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > index 8125b92..04ede1e 100644 > --- a/xen/arch/arm/time.c > +++ b/xen/arch/arm/time.c > @@ -223,11 +223,11 @@ static void vtimer_interrupt(int irq, void *dev_id, > struct cpu_user_regs *regs) > void __cpuinit route_timer_interrupt(void) > { > gic_route_dt_irq(&timer_irq[TIMER_PHYS_NONSECURE_PPI], > - 1u << smp_processor_id(), 0xa0); > + cpumask_of(smp_processor_id()), 0xa0); > gic_route_dt_irq(&timer_irq[TIMER_HYP_PPI], > - 1u << smp_processor_id(), 0xa0); > + cpumask_of(smp_processor_id()), 0xa0); > gic_route_dt_irq(&timer_irq[TIMER_VIRT_PPI], > - 1u << smp_processor_id(), 0xa0); > + cpumask_of(smp_processor_id()), 0xa0); > } > > /* Set up the timer interrupt on this CPU */ > diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h > index 90e887e..26b33bc 100644 > --- a/xen/include/asm-arm/gic.h > +++ b/xen/include/asm-arm/gic.h > @@ -146,7 +146,8 @@ extern void vgic_clear_pending_irqs(struct vcpu *v); > extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); > > /* Program the GIC to route an interrupt with a dt_irq */ > -extern void gic_route_dt_irq(const struct dt_irq *irq, unsigned int cpu_mask, > +extern void gic_route_dt_irq(const struct dt_irq *irq, > + const cpumask_t *cpu_mask, > unsigned int priority); > extern void gic_route_ppis(void); > extern void gic_route_spis(void); _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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