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[Xen-devel] [PATCH v2 0/5] xl: allow for node-wise specification of vcpu pinning



Hi all,

This is the second take of a patch that I submitted some time ago for allowing
specifying vcpu pinning taking NUMA nodes into account. IOW, something like
this:
 * "nodes:0-3": all pCPUs of nodes 0,1,2,3;
Â* "nodes:0-3,^node:2": all pCPUS of nodes 0,1,3;
Â* "1,nodes:1-2,^6": pCPU 1 plus all pCPUs of nodes 1,2
ÂÂ but not pCPU 6;

v1 was a single patch, this is a small series. It become necessary to do that
while coping with the review comments I got from IanJ. While at it, I am also
sending a small fix to the xl manpage, which is not related to the series, but
is still about vcpu pinning (something that I forgot to change when working on
NUMA-aware scheduling), as the first patch in the series itself.

I really believe I addressed all of Ian's comments, although, no, I haven't
converted the parsing to flex (which was not an hard requirement, AFAIUI),
because I don't think it is worthwhile in this case.

Let me know what you think about it.

Thanks and Regards,
Dario

---
Dario Faggioli (5):
      xl: update the manpage about "cpus=" and NUMA node-affinity
      libxl: introduce libxl_node_to_cpumap
      xl: allow for node-wise specification of vcpu pinning
      xl: implement and enable dryrun mode for `xl vcpu-pin'
      xl: test script for the cpumap parser (for vCPU pinning)


 docs/man/xl.cfg.pod.5              |   42 +++++--
 tools/libxl/check-xl-vcpupin-parse |  229 ++++++++++++++++++++++++++++++++++++
 tools/libxl/libxl_utils.c          |   22 +++
 tools/libxl/libxl_utils.h          |    3 
 tools/libxl/xl_cmdimpl.c           |  198 ++++++++++++++++++++++---------
 tools/libxl/xl_cmdtable.c          |    2 
 6 files changed, 432 insertions(+), 64 deletions(-)
 create mode 100755 tools/libxl/check-xl-vcpupin-parse

--
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)

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