Re: [Xen-devel] [PATCH] pl011: assert RTS signal in case the receiver uses flow control

[Andre Przywara <andre.przywara@xxxxxxxxxx>]

On 09/02/2013 06:21 PM, Tim Deegan wrote:
> At 16:51 +0200 on 02 Sep (1378140705), Andre Przywara wrote:
> > Although we do not support hardware flow control in the Xen driver
> > for the PL011 UART, the other end may be configured to use it.
> > In this case it waits in vain for the RTS signal to be asserted by
> > the host and will never transmit any characters.
> > This fixes the UART input on Calxeda Midway, which uses hardware
> > flow control for the serial-over-LAN functionality.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxxxxx>
> > ---
> >   xen/drivers/char/pl011.c         | 4 ++--
> >   xen/include/asm-arm/pl011-uart.h | 4 ++++
> >   2 files changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
> > index 3ec6e10..e340961 100644
> > --- a/xen/drivers/char/pl011.c
> > +++ b/xen/drivers/char/pl011.c
> > @@ -120,8 +120,8 @@ static void __init pl011_init_preirq(struct serial_port 
> > *port)
> >       pl011_write(uart, IMSC, 0);
> >       pl011_write(uart, ICR, ALLI);
> >
> > -    /* Enable the UART for RX and TX; no flow ctrl */
> > -    pl011_write(uart, CR, RXE | TXE | UARTEN);
> > +    /* Enable the UART for RX and TX; assert RTS in case the other end cares */
> > +    pl011_write(uart, CR, RTS | RXE | TXE | UARTEN);
> >   }
> >
> >   static void __init pl011_init_postirq(struct serial_port *port)
> > diff --git a/xen/include/asm-arm/pl011-uart.h b/xen/include/asm-arm/pl011-uart.h
> > index 3332c51..123f477 100644
> > --- a/xen/include/asm-arm/pl011-uart.h
> > +++ b/xen/include/asm-arm/pl011-uart.h
> > @@ -38,6 +38,10 @@
> >   #define DMACR  (0x48)
> >
> >   /* CR bits */
> > +#define CTSEN  (1<<15) /* automatic CTS hardware flow control */
> > +#define RTSEN  (1<<14) /* automatic RTS hardware flow control */
> Would this bit not be better than blindly setting RTS?
I don't think so. This sets and clears RTS according to the FIFO fill 
level. Since we don't claim to support h/w flow control, we better leave 
this disabled.
Just asserting RTS all of the time should have no influence on 
non-prepared devices[1]. So I will go with simply ORing in our requested 
bits and leave the flow-control bits as they have been setup before.
Regards,
Andre.

[1] 
http://git.denx.de/?p=u-boot.git;a=commit;h=10501df05e2d2eef501c92483c134d5f7c9da150 


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