Re: [Xen-devel] [PATCH 2/3] xen/arm64: resync atomics and spinlock asm with Linux

[Tim Deegan <tim@xxxxxxx>]

At 16:20 +0100 on 19 Jul (1374250809), Ian Campbell wrote:
> This picks up the changes from Linux commit 3a0310eb369a:
>     arm64: atomics: fix grossly inconsistent asm constraints for exclusives
> 
>     Our uses of inline asm constraints for atomic operations are fairly
>     wild and varied. We basically need to guarantee the following:
> 
>       1. Any instructions with barrier implications
>          (load-acquire/store-release) have a "memory" clobber
> 
>       2. When performing exclusive accesses, the addresing mode is generated
>          using the "Q" constraint
> 
>       3. Atomic blocks which use the condition flags, have a "cc" clobber
> 
>     This patch addresses these concerns which, as well as fixing the
>     semantics of the code, stops GCC complaining about impossible asm
>     constraints.
> 
>     Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
>     Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
> 
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

In so far as this is just pulling in upstream fixes to code we copied
from linux, Acked-by: Tim Deegan <tim@xxxxxxx>

But I don't understand the new 'memory' clobbers around in this patch.
Or rather, I don't understand why there are memory clobbers but not
DMBs.

The ARM ARM says: 

"The synchronization primitives follow the memory order model of the
 memory type accessed by the instructions. For this reason:
  - Portable code for claiming a spin-lock must include a Data
    Memory Barrier (DMB) operation, performed by a DMB instruction,
    between claiming the spin-lock and making any access that makes 
    use of the spin-lock.
  - Portable code for releasing a spin-lock must include a DMB
    instruction before writing to clear the spin-lock.
 This requirement applies to code using:
  - the Load-Exclusive/Store-Exclusive instruction pairs, for
    example LDREX/STREX
  - the deprecated synchronization primitives, SWP/SWPB."

Are the callers of these ops expected to put in the DMBs separately?

Tim.


_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel