Re: [Xen-devel] [PATCH v2] xen/arm: Implement MPIDR per VCPU

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Wed, 2013-07-17 at 11:02 +0100, Julien Grall wrote:
> On 07/17/2013 10:55 AM, Ian Campbell wrote:
> > On Mon, 2013-07-15 at 15:41 +0100, Julien Grall wrote:
> >> Use different affinity for each VCPU and always expose an SMP systems to
> >> the guest.
> >>
> >> Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
> > 
> > Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> > 
> > I would apply but it looks like it depends on your ACTLR patch, which I
> > had a comment on.
> 
> There is no dependency between the both patch, except the "diff context".
> 
> I can send a new patch.

I applied the ACTLR one but in the meantime I noticed an issue, I think.
[...]
> >> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> >> index 339b6e6..425eb71 100644
> >> --- a/xen/include/asm-arm/domain.h
> >> +++ b/xen/include/asm-arm/domain.h
> >> @@ -68,7 +68,6 @@ struct arch_domain
> >>  
> >>      /* Virtual CPUID */
> >>      uint32_t vpidr;
> >> -    register_t vmpidr;
> >>  
> >>      struct {
> >>          uint64_t offset;
> >> @@ -194,6 +193,7 @@ struct arch_vcpu
> >>  
> >>      /* CP 15 */
> >>      uint32_t csselr;
> >> +    uint32_t vmpidr;

This register is 64-bit on arm64 so it needs to stay a register_t, which
is consistent with the use of WRITE_SYSREG (as opposed to
WRITE_SYSREG32).

FYI the new bits are 39:32 == AFFR3 and in addition bit 31 (the
MPIDR_SMP bit) is always 1 on arm64. Since you only care about AFFR0 and
set SMP I don't think your code needs to change at all.

Ian.

> >>  
> >>      uint32_t gic_hcr, gic_vmcr, gic_apr;
> >>      uint32_t gic_lr[64];
> >> diff --git a/xen/include/asm-arm/processor.h 
> >> b/xen/include/asm-arm/processor.h
> >> index 1c9d793..5181e7b 100644
> >> --- a/xen/include/asm-arm/processor.h
> >> +++ b/xen/include/asm-arm/processor.h
> >> @@ -6,6 +6,12 @@
> >>  /* MIDR Main ID Register */
> >>  #define MIDR_MASK    0xff0ffff0
> >>  
> >> +/* MPIDR Multiprocessor Affinity Register */
> >> +#define MPIDR_UP            (1 << 30)
> >> +#define MPIDR_SMP           (1 << 31)
> >> +#define MPIDR_AFF0_SHIFT    (0)
> >> +#define MPIDR_AFF0_MASK     (0xff << MPIDR_AFF0_SHIFT)
> >> +
> >>  /* TTBCR Translation Table Base Control Register */
> >>  #define TTBCR_EAE    0x80000000
> >>  #define TTBCR_N_MASK 0x07
> > 
> > 
> 



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