Re: [Xen-devel] [PATCH 03/10] xen: arm: reduce instruction cache and tlb flushes to inner-shareable.

[Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>]

On Fri, 28 Jun 2013, Ian Campbell wrote:
> Now that Xen maps memory and performs pagetable walks as inner shareable we
> don't need to push updates down so far when modifying page tables etc.
> 
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

Acked-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>


>  xen/include/asm-arm/arm32/flushtlb.h |    4 ++--
>  xen/include/asm-arm/arm32/page.h     |    8 ++++----
>  xen/include/asm-arm/arm64/flushtlb.h |    4 ++--
>  xen/include/asm-arm/arm64/page.h     |    6 +++---
>  4 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/xen/include/asm-arm/arm32/flushtlb.h 
> b/xen/include/asm-arm/arm32/flushtlb.h
> index a258f58..14e8827 100644
> --- a/xen/include/asm-arm/arm32/flushtlb.h
> +++ b/xen/include/asm-arm/arm32/flushtlb.h
> @@ -6,7 +6,7 @@ static inline void flush_tlb_local(void)
>  {
>      dsb();
>  
> -    WRITE_CP32((uint32_t) 0, TLBIALL);
> +    WRITE_CP32((uint32_t) 0, TLBIALLIS);
>  
>      dsb();
>      isb();
> @@ -17,7 +17,7 @@ static inline void flush_tlb_all_local(void)
>  {
>      dsb();
>  
> -    WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
> +    WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS);
>  
>      dsb();
>      isb();
> diff --git a/xen/include/asm-arm/arm32/page.h 
> b/xen/include/asm-arm/arm32/page.h
> index 38bcffd..e573502 100644
> --- a/xen/include/asm-arm/arm32/page.h
> +++ b/xen/include/asm-arm/arm32/page.h
> @@ -39,8 +39,8 @@ static inline void flush_xen_text_tlb(void)
>      asm volatile (
>          "isb;"                        /* Ensure synchronization with 
> previous changes to text */
>          STORE_CP32(0, TLBIALLH)       /* Flush hypervisor TLB */
> -        STORE_CP32(0, ICIALLU)        /* Flush I-cache */
> -        STORE_CP32(0, BPIALL)         /* Flush branch predictor */
> +        STORE_CP32(0, ICIALLUIS)      /* Flush I-cache */
> +        STORE_CP32(0, BPIALLIS)       /* Flush branch predictor */
>          "dsb;"                        /* Ensure completion of TLB+BP flush */
>          "isb;"
>          : : "r" (r0) /*dummy*/ : "memory");
> @@ -54,7 +54,7 @@ static inline void flush_xen_data_tlb(void)
>  {
>      register unsigned long r0 asm ("r0");
>      asm volatile("dsb;" /* Ensure preceding are visible */
> -                 STORE_CP32(0, TLBIALLH)
> +                 STORE_CP32(0, TLBIALLHIS)
>                   "dsb;" /* Ensure completion of the TLB flush */
>                   "isb;"
>                   : : "r" (r0) /* dummy */: "memory");
> @@ -69,7 +69,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned 
> long va, unsigned long s
>      unsigned long end = va + size;
>      dsb(); /* Ensure preceding are visible */
>      while ( va < end ) {
> -        asm volatile(STORE_CP32(0, TLBIMVAH)
> +        asm volatile(STORE_CP32(0, TLBIMVAHIS)
>                       : : "r" (va) : "memory");
>          va += PAGE_SIZE;
>      }
> diff --git a/xen/include/asm-arm/arm64/flushtlb.h 
> b/xen/include/asm-arm/arm64/flushtlb.h
> index d0535a0..3a6d2cb 100644
> --- a/xen/include/asm-arm/arm64/flushtlb.h
> +++ b/xen/include/asm-arm/arm64/flushtlb.h
> @@ -6,7 +6,7 @@ static inline void flush_tlb_local(void)
>  {
>      asm volatile(
>          "dsb sy;"
> -        "tlbi vmalle1;"
> +        "tlbi vmalle1is;"
>          "dsb sy;"
>          "isb;"
>          : : : "memory");
> @@ -17,7 +17,7 @@ static inline void flush_tlb_all_local(void)
>  {
>      asm volatile(
>          "dsb sy;"
> -        "tlbi alle1;"
> +        "tlbi alle1is;"
>          "dsb sy;"
>          "isb;"
>          : : : "memory");
> diff --git a/xen/include/asm-arm/arm64/page.h 
> b/xen/include/asm-arm/arm64/page.h
> index bd48fe3..28748d3 100644
> --- a/xen/include/asm-arm/arm64/page.h
> +++ b/xen/include/asm-arm/arm64/page.h
> @@ -33,7 +33,7 @@ static inline void flush_xen_text_tlb(void)
>      asm volatile (
>          "isb;"       /* Ensure synchronization with previous changes to text 
> */
>          "tlbi   alle2;"                 /* Flush hypervisor TLB */
> -        "ic     iallu;"                 /* Flush I-cache */
> +        "ic     ialluis;"               /* Flush I-cache */
>          "dsb    sy;"                    /* Ensure completion of TLB flush */
>          "isb;"
>          : : : "memory");
> @@ -47,7 +47,7 @@ static inline void flush_xen_data_tlb(void)
>  {
>      asm volatile (
>          "dsb    sy;"                    /* Ensure visibility of PTE writes */
> -        "tlbi   alle2;"                 /* Flush hypervisor TLB */
> +        "tlbi   alle2is;"               /* Flush hypervisor TLB */
>          "dsb    sy;"                    /* Ensure completion of TLB flush */
>          "isb;"
>          : : : "memory");
> @@ -62,7 +62,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned 
> long va, unsigned long s
>      unsigned long end = va + size;
>      dsb(); /* Ensure preceding are visible */
>      while ( va < end ) {
> -        asm volatile("tlbi vae2, %0;"
> +        asm volatile("tlbi vae2is, %0;"
>                       : : "r" (va>>PAGE_SHIFT) : "memory");
>          va += PAGE_SIZE;
>      }
> -- 
> 1.7.2.5
> 

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